AES/UNMASKED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	1.133m	64.148us	1	1	100.00
V1	smoke	aes_smoke	1.783m	77.545us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	30.000s	68.432us	5	5	100.00
V1	csr_rw	aes_csr_rw	34.000s	84.768us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	55.000s	392.328us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	33.000s	1.431ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	34.000s	63.130us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	34.000s	84.768us	20	20	100.00
		aes_csr_aliasing	33.000s	1.431ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.783m	77.545us	50	50	100.00
		aes_config_error	1.117m	117.178us	50	50	100.00
		aes_stress	1.933m	195.111us	50	50	100.00
V2	key_length	aes_smoke	1.783m	77.545us	50	50	100.00
		aes_config_error	1.117m	117.178us	50	50	100.00
		aes_stress	1.933m	195.111us	50	50	100.00
V2	back2back	aes_stress	1.933m	195.111us	50	50	100.00
		aes_b2b	1.817m	110.562us	50	50	100.00
V2	backpressure	aes_stress	1.933m	195.111us	50	50	100.00
V2	multi_message	aes_smoke	1.783m	77.545us	50	50	100.00
		aes_config_error	1.117m	117.178us	50	50	100.00
		aes_stress	1.933m	195.111us	50	50	100.00
		aes_alert_reset	1.683m	163.657us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.750m	81.809us	50	50	100.00
		aes_config_error	1.117m	117.178us	50	50	100.00
		aes_alert_reset	1.683m	163.657us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.533m	63.348us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	513.249us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.683m	163.657us	50	50	100.00
V2	stress	aes_stress	1.933m	195.111us	50	50	100.00
V2	sideload	aes_stress	1.933m	195.111us	50	50	100.00
		aes_sideload	1.533m	99.920us	50	50	100.00
V2	deinitialization	aes_deinit	2.367m	112.915us	50	50	100.00
V2	stress_all	aes_stress_all	1.500m	1.699ms	10	10	100.00
V2	alert_test	aes_alert_test	1.950m	73.588us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	34.000s	97.390us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	34.000s	97.390us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	30.000s	68.432us	5	5	100.00
		aes_csr_rw	34.000s	84.768us	20	20	100.00
		aes_csr_aliasing	33.000s	1.431ms	5	5	100.00
		aes_same_csr_outstanding	33.000s	128.282us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	30.000s	68.432us	5	5	100.00
		aes_csr_rw	34.000s	84.768us	20	20	100.00
		aes_csr_aliasing	33.000s	1.431ms	5	5	100.00
		aes_same_csr_outstanding	33.000s	128.282us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.933m	89.494us	50	50	100.00
V2S	fault_inject	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	32.000s	77.824us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	32.000s	77.824us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	32.000s	77.824us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	32.000s	77.824us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	36.000s	204.550us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.433m	381.696us	5	5	100.00
		aes_tl_intg_err	1.233m	104.937us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.233m	104.937us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.683m	163.657us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	32.000s	77.824us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.783m	77.545us	50	50	100.00
		aes_stress	1.933m	195.111us	50	50	100.00
		aes_alert_reset	1.683m	163.657us	50	50	100.00
		aes_core_fi	1.933m	263.047us	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	32.000s	77.824us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.733m	77.987us	50	50	100.00
		aes_stress	1.933m	195.111us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.933m	195.111us	50	50	100.00
		aes_sideload	1.533m	99.920us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.733m	77.987us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.733m	77.987us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.733m	77.987us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.733m	77.987us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.733m	77.987us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.933m	195.111us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.933m	195.111us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.000m	177.898us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
		aes_ctr_fi	59.000s	59.365us	47	50	94.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.000m	177.898us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	94.465us	294	350	84.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.000m	177.898us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_ctr_fi	59.000s	59.365us	47	50	94.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
		aes_ctr_fi	59.000s	59.365us	47	50	94.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.683m	163.657us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
		aes_ctr_fi	59.000s	59.365us	47	50	94.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
		aes_ctr_fi	59.000s	59.365us	47	50	94.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_ctr_fi	59.000s	59.365us	47	50	94.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.000m	177.898us	49	50	98.00
		aes_control_fi	59.000s	49.285us	247	300	82.33
		aes_cipher_fi	59.000s	94.465us	294	350	84.00
V2S		TOTAL			868	985	88.12
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.650m	4.357ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1475	1602	92.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.44	94.22	98.77	93.74	97.72	93.33	98.66	96.21

Failure Buckets

Job timed out after * minutes has 94 failures:
- Test aes_ctr_fi has 3 failures.
  - 0.aes_ctr_fi.101582474532354475324419892981461834005256895509258461619134504113347102807842
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/0.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 19.aes_ctr_fi.108343608408664952836021348075659276009121574483701423144682092239467177294164
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/19.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 1 more failures.
- Test aes_control_fi has 44 failures.
  - 3.aes_control_fi.89830111475121996861977542925792125518351239462655598144543843452342629189346
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 26.aes_control_fi.34843315803755972965207440932267630349946589343024933393112901046901460041742
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 42 more failures.
- Test aes_cipher_fi has 47 failures.
  - 9.aes_cipher_fi.13066485738385736043112011189771265266474818478863659275857827871835614632014
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 11.aes_cipher_fi.71106497181728567031059142801665102591997200292966739779675079421345376993033
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 45 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 11.aes_control_fi.60052426324897029643825584589128329590452261639116354879561316099140209037800
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005304839 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005304839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.aes_control_fi.9770950693702053416509628513338504882543172703201319516371346719516543797990
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004730754 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004730754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 44.aes_cipher_fi.115114532703621667784589178253664471685587103514081822249374225044098479614462
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008338861 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008338861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_cipher_fi.68225747718545486159137642719631854335244336104816670393795867879205837229798
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10029810646 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029810646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.14617216904900004093264180864916674269689930256934144780357907604210171676429
Line 154, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 473724290 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 473724290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.7812003616754504956581167091363452853885343138386389152643316005064236858890
Line 354, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  82978369 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  82978369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.90845562058833953951428792442182066980370854557663693498449078843932346657053
Line 616, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 734423876 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 734423876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.27735603416866601077832289211643464260682744371893968121792946819442177274766
Line 1078, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1390436607 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1390436607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 9.aes_core_fi.37076532267204556835600498454370870621493451125398656130076957873483971472853
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008010760 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008010760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_core_fi.92772284313866808092773745234510818889093864101951949851423475249244291149482
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009305798 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009305798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 5.aes_fi.72550267090557980739199993924477713398779903030120147350148622647284337469639
    Line 7471, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_unmasked-sim-xcelium/5.aes_fi/latest/run.log
```
  UVM_FATAL @ 177897582 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 177897582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```