AES/UNMASKED Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: XCELIUM

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	62.382us	1	1	100.00
V1	smoke	aes_smoke	1.867m	76.316us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.017m	81.902us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.017m	53.478us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.017m	189.575us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.500m	69.575us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.033m	70.099us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.017m	53.478us	20	20	100.00
		aes_csr_aliasing	1.500m	69.575us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.867m	76.316us	50	50	100.00
		aes_config_error	1.700m	205.205us	50	50	100.00
		aes_stress	1.683m	83.140us	50	50	100.00
V2	key_length	aes_smoke	1.867m	76.316us	50	50	100.00
		aes_config_error	1.700m	205.205us	50	50	100.00
		aes_stress	1.683m	83.140us	50	50	100.00
V2	back2back	aes_stress	1.683m	83.140us	50	50	100.00
		aes_b2b	2.000m	100.687us	50	50	100.00
V2	backpressure	aes_stress	1.683m	83.140us	50	50	100.00
V2	multi_message	aes_smoke	1.867m	76.316us	50	50	100.00
		aes_config_error	1.700m	205.205us	50	50	100.00
		aes_stress	1.683m	83.140us	50	50	100.00
		aes_alert_reset	1.433m	103.158us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.917m	55.616us	50	50	100.00
		aes_config_error	1.700m	205.205us	50	50	100.00
		aes_alert_reset	1.433m	103.158us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.667m	159.428us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	114.747us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.433m	103.158us	50	50	100.00
V2	stress	aes_stress	1.683m	83.140us	50	50	100.00
V2	sideload	aes_stress	1.683m	83.140us	50	50	100.00
		aes_sideload	1.533m	135.571us	50	50	100.00
V2	deinitialization	aes_deinit	1.450m	139.141us	50	50	100.00
V2	stress_all	aes_stress_all	1.317m	3.182ms	10	10	100.00
V2	alert_test	aes_alert_test	2.033m	55.059us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.400m	171.018us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.400m	171.018us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.017m	81.902us	5	5	100.00
		aes_csr_rw	1.017m	53.478us	20	20	100.00
		aes_csr_aliasing	1.500m	69.575us	5	5	100.00
		aes_same_csr_outstanding	1.500m	212.773us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.017m	81.902us	5	5	100.00
		aes_csr_rw	1.017m	53.478us	20	20	100.00
		aes_csr_aliasing	1.500m	69.575us	5	5	100.00
		aes_same_csr_outstanding	1.500m	212.773us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.467m	149.229us	50	50	100.00
V2S	fault_inject	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.000m	67.673us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.000m	67.673us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.000m	67.673us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.000m	67.673us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.533m	157.996us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.200m	673.120us	5	5	100.00
		aes_tl_intg_err	1.500m	197.217us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.500m	197.217us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.433m	103.158us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.000m	67.673us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.867m	76.316us	50	50	100.00
		aes_stress	1.683m	83.140us	50	50	100.00
		aes_alert_reset	1.433m	103.158us	50	50	100.00
		aes_core_fi	3.067m	10.018ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.000m	67.673us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.617m	84.862us	50	50	100.00
		aes_stress	1.683m	83.140us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.683m	83.140us	50	50	100.00
		aes_sideload	1.533m	135.571us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.617m	84.862us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.617m	84.862us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.617m	84.862us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.617m	84.862us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.617m	84.862us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.683m	83.140us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.683m	83.140us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.883m	370.513us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
		aes_ctr_fi	1.000m	137.280us	45	50	90.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.883m	370.513us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	65.614ms	296	350	84.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.883m	370.513us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_ctr_fi	1.000m	137.280us	45	50	90.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
		aes_ctr_fi	1.000m	137.280us	45	50	90.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.433m	103.158us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
		aes_ctr_fi	1.000m	137.280us	45	50	90.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
		aes_ctr_fi	1.000m	137.280us	45	50	90.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_ctr_fi	1.000m	137.280us	45	50	90.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.883m	370.513us	50	50	100.00
		aes_control_fi	59.000s	50.370us	233	300	77.67
		aes_cipher_fi	1.000m	65.614ms	296	350	84.57
V2S		TOTAL			854	985	86.70
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.133m	613.256us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1461	1602	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.27	97.54	94.43	98.81	93.83	97.72	92.59	98.85	97.60

Failure Buckets

Job timed out after * minutes has 112 failures:
- Test aes_control_fi has 59 failures.
  - 3.aes_control_fi.40153032747270434120604155779768916283635173443568511192545099650697861518185
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 4.aes_control_fi.111734473528693143860984565660319720534567722835265232590212127066345963639457
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 57 more failures.
- Test aes_cipher_fi has 48 failures.
  - 3.aes_cipher_fi.28840266341637919198022086141662444723702664449754703680813324148472152172602
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 4.aes_cipher_fi.110645344693564383034627779615126969984920970235492075213602872293200194761457
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 46 more failures.
- Test aes_ctr_fi has 5 failures.
  - 3.aes_ctr_fi.45364489493797628797984421376370547615955865199621139604215251844755145941014
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/3.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 15.aes_ctr_fi.76195377852519203824870562965284586966438554731020716599312725907655323954417
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/15.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 97.aes_control_fi.27244342586096495077071889274205443349957989210670158209223230787164416728769
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009680263 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009680263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 124.aes_control_fi.42261768949966970288120860954820634514692245834271835085486626449835988312748
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/124.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003913988 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003913988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.45262124755820643822073572812826112043444928817095390320846096823268619909490
Line 487, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 999538624 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 999538624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.47314968492801682050399743279867769267358391197282953368212560376761912362494
Line 153, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   7802385 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   7802385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 183.aes_cipher_fi.85035907450536074917126690528674889476947840742750462459803089824263385480200
    Line 123, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/183.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007756123 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007756123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 204.aes_cipher_fi.20669531912053397173795129234588728406389403263417107322339423658664952527247
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/204.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003983162 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003983162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.16334254829707453016023183135632852289390200699946018784488978274231815260242
    Line 591, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 199110045 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 199110045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.38007982014815780040157641162666669540691742276371905118261113529312803593290
    Line 152, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  64576025 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  64576025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 11.aes_core_fi.96552406535355101306642721825627933188071054020619537929021782404923102239847
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030050667 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030050667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_core_fi.26656126683227738494783664492892274884951309170595541246220190659387319840688
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020686018 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020686018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 18.aes_core_fi.11903770391516633399628053004460686931797527822542579029026315252611658406973
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012127496 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012127496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_core_fi.107625494456259177039415402583425977040375271779291264280332027121943802775156
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011476429 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011476429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.104403048140624247512926046034911231439789174341845153701803022734924222764496
    Line 377, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 613256349 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 613256349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.18293531488307569102768879467025007770012008054543594987825133675411602013834
    Line 732, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 220268253 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 220257836 PS)
  UVM_ERROR @ 220268253 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 220268253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 41.aes_core_fi.57781627060104967614728578459688471930866085926004891911096683562708761719689
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017645030 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf34b3a84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10017645030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```