AES/UNMASKED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	51.429us	1	1	100.00
V1	smoke	aes_smoke	1.917m	102.634us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	89.702us	5	5	100.00
V1	csr_rw	aes_csr_rw	19.000s	51.751us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.655ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	258.163us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	15.000s	64.539us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	19.000s	51.751us	20	20	100.00
		aes_csr_aliasing	7.000s	258.163us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.917m	102.634us	50	50	100.00
		aes_config_error	1.933m	177.066us	50	50	100.00
		aes_stress	1.617m	367.991us	50	50	100.00
V2	key_length	aes_smoke	1.917m	102.634us	50	50	100.00
		aes_config_error	1.933m	177.066us	50	50	100.00
		aes_stress	1.617m	367.991us	50	50	100.00
V2	back2back	aes_stress	1.617m	367.991us	50	50	100.00
		aes_b2b	1.933m	100.743us	50	50	100.00
V2	backpressure	aes_stress	1.617m	367.991us	50	50	100.00
V2	multi_message	aes_smoke	1.917m	102.634us	50	50	100.00
		aes_config_error	1.933m	177.066us	50	50	100.00
		aes_stress	1.617m	367.991us	50	50	100.00
		aes_alert_reset	1.883m	396.592us	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.017m	54.317us	50	50	100.00
		aes_config_error	1.933m	177.066us	50	50	100.00
		aes_alert_reset	1.883m	396.592us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.900m	153.844us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	584.243us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.883m	396.592us	50	50	100.00
V2	stress	aes_stress	1.617m	367.991us	50	50	100.00
V2	sideload	aes_stress	1.617m	367.991us	50	50	100.00
		aes_sideload	1.950m	69.982us	50	50	100.00
V2	deinitialization	aes_deinit	1.950m	115.574us	50	50	100.00
V2	stress_all	aes_stress_all	1.200m	3.436ms	10	10	100.00
V2	alert_test	aes_alert_test	1.750m	76.323us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	20.000s	81.663us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	20.000s	81.663us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	89.702us	5	5	100.00
		aes_csr_rw	19.000s	51.751us	20	20	100.00
		aes_csr_aliasing	7.000s	258.163us	5	5	100.00
		aes_same_csr_outstanding	15.000s	79.404us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	89.702us	5	5	100.00
		aes_csr_rw	19.000s	51.751us	20	20	100.00
		aes_csr_aliasing	7.000s	258.163us	5	5	100.00
		aes_same_csr_outstanding	15.000s	79.404us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.950m	172.360us	50	50	100.00
V2S	fault_inject	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	19.000s	97.641us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	19.000s	97.641us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	19.000s	97.641us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	19.000s	97.641us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	20.000s	394.720us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	55.000s	253.205us	5	5	100.00
		aes_tl_intg_err	19.000s	130.514us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	19.000s	130.514us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.883m	396.592us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	19.000s	97.641us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.917m	102.634us	50	50	100.00
		aes_stress	1.617m	367.991us	50	50	100.00
		aes_alert_reset	1.883m	396.592us	50	50	100.00
		aes_core_fi	3.233m	10.015ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	19.000s	97.641us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.533m	102.100us	50	50	100.00
		aes_stress	1.617m	367.991us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.617m	367.991us	50	50	100.00
		aes_sideload	1.950m	69.982us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.533m	102.100us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.533m	102.100us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.533m	102.100us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.533m	102.100us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.533m	102.100us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.617m	367.991us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.617m	367.991us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.800m	118.907us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
		aes_ctr_fi	1.000m	175.677us	44	50	88.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.800m	118.907us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	91.677us	285	350	81.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.800m	118.907us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_ctr_fi	1.000m	175.677us	44	50	88.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
		aes_ctr_fi	1.000m	175.677us	44	50	88.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.883m	396.592us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
		aes_ctr_fi	1.000m	175.677us	44	50	88.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
		aes_ctr_fi	1.000m	175.677us	44	50	88.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_ctr_fi	1.000m	175.677us	44	50	88.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.800m	118.907us	50	50	100.00
		aes_control_fi	1.000m	49.976us	237	300	79.00
		aes_cipher_fi	1.000m	91.677us	285	350	81.43
V2S		TOTAL			848	985	86.09
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.033m	791.879us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1455	1602	90.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.41	94.14	98.77	93.60	97.64	91.11	98.85	97.41

Failure Buckets

Job timed out after * minutes has 120 failures:
- Test aes_cipher_fi has 57 failures.
  - 1.aes_cipher_fi.82243431096113423280375949429916483352695836876660087910589990063883611147746
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_cipher_fi.75158313332053383771630547020164331653901807231080596724202744185416743257323
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 55 more failures.
- Test aes_control_fi has 57 failures.
  - 2.aes_control_fi.3889388795886423993793120223889938950560312968914475790491219251054872151217
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 12.aes_control_fi.56422889724787904423969451627677618243681328938332105706789292600664875607019
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 55 more failures.
- Test aes_ctr_fi has 6 failures.
  - 11.aes_ctr_fi.18300958267134708191856885187848113786370357099175926714462125278738029453902
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/11.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_ctr_fi.107959721589552739603783939044388192443554925380226276808594560817478236127310
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 8.aes_cipher_fi.38870972388645188891826240718070013691443150632762115814972841339456437117906
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005772855 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005772855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.aes_cipher_fi.70363104733631854920671330427479872010147689729328901721575146321417248569266
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006831865 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006831865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 54.aes_control_fi.75804094140353424813461152546315370920429431344146780895676729771140643119938
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003295006 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003295006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.aes_control_fi.78272475257999897907943690101363079864466019701727265960070078806508207505412
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012720967 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012720967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.78315392477144193964383874320135189163967096441690178088316052667765284759982
Line 1467, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 457955887 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 457955887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.101955370108515052521543328665365158413766352452667713595993959665394876539431
Line 664, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 791879441 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 791879441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.100068784181911636449891651060208039691288197091472170624551665552776784918074
Line 373, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 919582530 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 919582530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.87390752691952821923557933817981689240758586932931723746198891507805846266227
Line 1049, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3707808797 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3707808797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 12.aes_core_fi.33164826927944320387614749240274454701338626438072951051165492105066665707192
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005776112 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005776112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_core_fi.41207114746078477037818965241279331574942182583057386306054568753517328966779
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004545925 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004545925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 14.aes_core_fi.98020243557306051257204893841529340324642620516033556629055060402602742122998
    Line 123, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014911669 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xa1975c84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10014911669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```