AES/UNMASKED Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	99.427us	1	1	100.00
V1	smoke	aes_smoke	1.467m	98.313us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	59.561us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	178.712us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	971.093us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	157.227us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	136.204us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	178.712us	20	20	100.00
		aes_csr_aliasing	6.000s	157.227us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.467m	98.313us	50	50	100.00
		aes_config_error	1.533m	194.067us	50	50	100.00
		aes_stress	1.450m	135.245us	50	50	100.00
V2	key_length	aes_smoke	1.467m	98.313us	50	50	100.00
		aes_config_error	1.533m	194.067us	50	50	100.00
		aes_stress	1.450m	135.245us	50	50	100.00
V2	back2back	aes_stress	1.450m	135.245us	50	50	100.00
		aes_b2b	1.467m	56.643us	50	50	100.00
V2	backpressure	aes_stress	1.450m	135.245us	50	50	100.00
V2	multi_message	aes_smoke	1.467m	98.313us	50	50	100.00
		aes_config_error	1.533m	194.067us	50	50	100.00
		aes_stress	1.450m	135.245us	50	50	100.00
		aes_alert_reset	1.433m	62.733us	49	50	98.00
V2	failure_test	aes_man_cfg_err	1.550m	104.321us	50	50	100.00
		aes_config_error	1.533m	194.067us	50	50	100.00
		aes_alert_reset	1.433m	62.733us	49	50	98.00
V2	trigger_clear_test	aes_clear	1.417m	88.615us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	156.057us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.433m	62.733us	49	50	98.00
V2	stress	aes_stress	1.450m	135.245us	50	50	100.00
V2	sideload	aes_stress	1.450m	135.245us	50	50	100.00
		aes_sideload	1.517m	76.299us	50	50	100.00
V2	deinitialization	aes_deinit	1.550m	72.258us	50	50	100.00
V2	stress_all	aes_stress_all	1.450m	755.756us	9	10	90.00
V2	alert_test	aes_alert_test	1.467m	74.893us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	215.831us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	215.831us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	59.561us	5	5	100.00
		aes_csr_rw	4.000s	178.712us	20	20	100.00
		aes_csr_aliasing	6.000s	157.227us	5	5	100.00
		aes_same_csr_outstanding	5.000s	127.958us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	59.561us	5	5	100.00
		aes_csr_rw	4.000s	178.712us	20	20	100.00
		aes_csr_aliasing	6.000s	157.227us	5	5	100.00
		aes_same_csr_outstanding	5.000s	127.958us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	1.517m	84.202us	50	50	100.00
V2S	fault_inject	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	52.852us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	52.852us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	52.852us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	52.852us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	484.198us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	28.000s	652.200us	5	5	100.00
		aes_tl_intg_err	7.000s	673.565us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	673.565us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.433m	62.733us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	52.852us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.467m	98.313us	50	50	100.00
		aes_stress	1.450m	135.245us	50	50	100.00
		aes_alert_reset	1.433m	62.733us	49	50	98.00
		aes_core_fi	2.117m	10.010ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	52.852us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.533m	59.152us	50	50	100.00
		aes_stress	1.450m	135.245us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.450m	135.245us	50	50	100.00
		aes_sideload	1.517m	76.299us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.533m	59.152us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.533m	59.152us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.533m	59.152us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.533m	59.152us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.533m	59.152us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.450m	135.245us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.450m	135.245us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.450m	364.914us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
		aes_ctr_fi	50.000s	66.475us	40	50	80.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.450m	364.914us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.033m	57.039us	263	350	75.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.450m	364.914us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_ctr_fi	50.000s	66.475us	40	50	80.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
		aes_ctr_fi	50.000s	66.475us	40	50	80.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.433m	62.733us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
		aes_ctr_fi	50.000s	66.475us	40	50	80.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
		aes_ctr_fi	50.000s	66.475us	40	50	80.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_ctr_fi	50.000s	66.475us	40	50	80.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.450m	364.914us	50	50	100.00
		aes_control_fi	59.000s	79.134us	233	300	77.67
		aes_cipher_fi	1.033m	57.039us	263	350	75.14
V2S		TOTAL			817	985	82.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.417m	77.401us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1422	1602	88.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.27	97.54	94.43	98.75	93.94	97.72	91.11	98.85	98.60

Failure Buckets

Job timed out after * minutes has 147 failures:
- Test aes_cipher_fi has 77 failures.
  - 1.aes_cipher_fi.76563645049950342506072276756315884625087648898487432535282965788355630837130
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 9.aes_cipher_fi.9463519482060936874383969459490513770341523120409714773163602325908706815594
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 75 more failures.
- Test aes_control_fi has 60 failures.
  - 9.aes_control_fi.77183448211953649060790718157252132476372412930790689725763301508134681077372
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 10.aes_control_fi.16515713684029490396188068056762444164025923505954955895848787489650713675884
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 58 more failures.
- Test aes_ctr_fi has 10 failures.
  - 9.aes_ctr_fi.61884601209835751911040179827028408530399803945527994494447100662660671221734
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/9.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 10.aes_ctr_fi.69994558858798840322182404141386001438312440589478386013463609090773707928036
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/10.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 30.aes_cipher_fi.21358958951946948550603065987672836821012370141781996089739076783949792633158
    Line 125, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013291147 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013291147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_cipher_fi.98894684465237123406343817484818139096573697046302965136848788332532703919541
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016526222 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016526222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.26961647579645110998426768189882640602546405459851863240310774863831496112788
Line 1389, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1540285097 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1540285097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.21653390577630903148244984595751597518149200269881732669765235088399569021440
Line 739, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 650536111 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 650536111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 98.aes_control_fi.76133097176737596285766105044562992755718332945771022420128422633293996940263
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/98.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010200649 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010200649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 104.aes_control_fi.34773819338802274624710260406677443380280309255085918916440935279784665286862
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/104.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011311816 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011311816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all has 1 failures.

2.aes_stress_all.108903722575271841008113002769234597245482182371271062414442846064456333458358
Line 53154, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/2.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 388093679 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 388073679 PS)
  UVM_ERROR @ 388093679 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 388093679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 1 failures.

5.aes_alert_reset.21159473685298431642805716429858639089209207251147313451692033416685960427861
Line 2812, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/5.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 37091346 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 37051346 PS)
  UVM_ERROR @  37091346 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  37091346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 30.aes_core_fi.37085524492549190372934539998975410966384587211371854313561355964427988550409
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006391283 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006391283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.35871697004083957900906468246171964725317536291040119721852659415087446049192
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008752142 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008752142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 60.aes_core_fi.22493812692615604934868522913112378971556319912934699135313555732484396212823
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010361325 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010361325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.aes_core_fi.15773439074736808625925410444595411051714260760679749272923136472213988748892
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019869675 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019869675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.91067141335288879478214517122886509417622339490539039515907332265934279416494
    Line 165, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  18932015 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  18932015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 4.aes_cipher_fi.23423625489123184621714534517788570074133827897705518614229157639554910225896
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.34400147911795711001359841393441319765021686224024961184739003637982546107876
    Line 203, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 222701161 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 222701161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```