AON_TIMER Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.380s	550.778us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.410s	1.244ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	499.960us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	8.130s	5.972ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.360s	504.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.400s	479.837us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	499.960us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	504.976us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.150s	449.087us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.110s	445.161us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.376m	53.400ms	50	50	100.00
V2	jump	aon_timer_jump	1.560s	642.942us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.787m	558.105ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.320s	511.696us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.840s	580.352us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.840s	580.352us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.410s	1.244ms	5	5	100.00
		aon_timer_csr_rw	1.380s	499.960us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	504.976us	5	5	100.00
		aon_timer_same_csr_outstanding	5.530s	1.986ms	18	20	90.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.410s	1.244ms	5	5	100.00
		aon_timer_csr_rw	1.380s	499.960us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	504.976us	5	5	100.00
		aon_timer_same_csr_outstanding	5.530s	1.986ms	18	20	90.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	4.210s	8.292ms	5	5	100.00
		aon_timer_tl_intg_err	13.920s	7.873ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.920s	7.873ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.165m	270.253ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			428	430	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 2 failures:

Test aon_timer_same_csr_outstanding has 2 failures.

7.aon_timer_same_csr_outstanding.1053327816
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 1838795438 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 1838795438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_same_csr_outstanding.2984984084
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 1282095079 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 1282095079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---