AON_TIMER Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.460s 582.897us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.590s 1.333ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.380s 533.896us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 15.310s 11.594ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.090s 534.521us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.520s 576.770us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.380s 533.896us 20 20 100.00
aon_timer_csr_aliasing 1.090s 534.521us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.170s 408.433us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.260s 455.567us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.173m 44.906ms 50 50 100.00
V2 jump aon_timer_jump 1.590s 602.292us 50 50 100.00
V2 stress_all aon_timer_stress_all 16.473m 663.644ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.290s 496.751us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.880s 574.095us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.880s 574.095us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.590s 1.333ms 5 5 100.00
aon_timer_csr_rw 1.380s 533.896us 20 20 100.00
aon_timer_csr_aliasing 1.090s 534.521us 5 5 100.00
aon_timer_same_csr_outstanding 6.060s 2.218ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.590s 1.333ms 5 5 100.00
aon_timer_csr_rw 1.380s 533.896us 20 20 100.00
aon_timer_csr_aliasing 1.090s 534.521us 5 5 100.00
aon_timer_same_csr_outstanding 6.060s 2.218ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 12.790s 7.122ms 5 5 100.00
aon_timer_tl_intg_err 15.230s 8.795ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 15.230s 8.795ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 17.300m 181.855ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.56 99.82 95.31 100.00 -- 99.35 100.00 96.90

Past Results