AON_TIMER Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	550.184us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.460s	1.153ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.480s	523.294us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.290s	13.942ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.370s	460.192us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	573.655us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.480s	523.294us	20	20	100.00
		aon_timer_csr_aliasing	1.370s	460.192us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.220s	477.956us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	514.670us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.494m	61.589ms	50	50	100.00
V2	jump	aon_timer_jump	1.530s	594.743us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.763m	289.284ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.340s	502.665us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.350s	621.483us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.350s	621.483us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.460s	1.153ms	5	5	100.00
		aon_timer_csr_rw	1.480s	523.294us	20	20	100.00
		aon_timer_csr_aliasing	1.370s	460.192us	5	5	100.00
		aon_timer_same_csr_outstanding	4.340s	2.601ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.460s	1.153ms	5	5	100.00
		aon_timer_csr_rw	1.480s	523.294us	20	20	100.00
		aon_timer_csr_aliasing	1.370s	460.192us	5	5	100.00
		aon_timer_same_csr_outstanding	4.340s	2.601ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	13.010s	7.674ms	5	5	100.00
		aon_timer_tl_intg_err	14.120s	8.654ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.120s	8.654ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	18.981m	163.367ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:461) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 9 failures.

0.aon_timer_stress_all_with_rand_reset.16300799005786123849478339954874828580197144459641802012454462606085161704888
Line 971, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 55070728448 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 55070728448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aon_timer_stress_all_with_rand_reset.3719593031250184053389542155251711443729664061903057648659779318132372827351
Line 259, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 489691588 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 489691588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aon_timer_stress_all has 4 failures.

2.aon_timer_stress_all.31516687352315447080979277055283130864436741379425913594073242799364824351678
Line 268, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1398334200 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1398334200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aon_timer_stress_all.46819916286974814626972927248000604921895120129167049792048653143427637551345
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 37650882289 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 37650882289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.