AON_TIMER Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.590s	616.810us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.310s	1.196ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	471.340us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.190s	13.919ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.390s	514.417us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.490s	605.584us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	471.340us	20	20	100.00
		aon_timer_csr_aliasing	1.390s	514.417us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.170s	499.597us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.260s	409.820us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.375m	55.604ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	565.649us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.977m	339.943ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.380s	518.808us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.970s	545.896us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.970s	545.896us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.310s	1.196ms	5	5	100.00
		aon_timer_csr_rw	1.350s	471.340us	20	20	100.00
		aon_timer_csr_aliasing	1.390s	514.417us	5	5	100.00
		aon_timer_same_csr_outstanding	6.250s	2.226ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.310s	1.196ms	5	5	100.00
		aon_timer_csr_rw	1.350s	471.340us	20	20	100.00
		aon_timer_csr_aliasing	1.390s	514.417us	5	5	100.00
		aon_timer_same_csr_outstanding	6.250s	2.226ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	4.180s	8.111ms	5	5	100.00
		aon_timer_tl_intg_err	12.630s	8.065ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.630s	8.065ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.060m	486.137ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

6.aon_timer_stress_all_with_rand_reset.11956270976206401107205513502969006387314610611889470392089084508875415724523
Line 484, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 42357341311 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 42357341311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all_with_rand_reset.36541549467923049760752807324392055016750782801120987713716204210238322700161
Line 532, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30259819511 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 30259819511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 1 failures.

43.aon_timer_stress_all.44896208284117042401388292624225341539349326504404542878799830794779228285024
Line 263, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 882212915 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 882212915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---