AON_TIMER Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.420s	502.523us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.890s	936.625us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	497.997us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.470s	10.172ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.450s	515.562us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.430s	541.339us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	497.997us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	515.562us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.110s	450.075us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.970s	276.101us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.216m	52.902ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	592.961us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.442m	352.337ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.240s	512.639us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.680s	560.491us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.680s	560.491us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.890s	936.625us	5	5	100.00
		aon_timer_csr_rw	1.370s	497.997us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	515.562us	5	5	100.00
		aon_timer_same_csr_outstanding	8.320s	2.461ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.890s	936.625us	5	5	100.00
		aon_timer_csr_rw	1.370s	497.997us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	515.562us	5	5	100.00
		aon_timer_same_csr_outstanding	8.320s	2.461ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	7.820s	4.248ms	5	5	100.00
		aon_timer_tl_intg_err	13.100s	7.720ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.100s	7.720ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.224m	370.302ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all has 3 failures.

4.aon_timer_stress_all.55245130126840542004316250573543858632509299204379606438471896887413897278027
Line 291, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 171988587254 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 171988587254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all.71313718160633306614900528241662192859160623543791181318050961356065547394015
Line 266, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 863151502 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 863151502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 7 failures.

14.aon_timer_stress_all_with_rand_reset.8561607211828176501827329467889781103584300530523838226912582627710094533296
Line 754, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 120681664274 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 120681664274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.aon_timer_stress_all_with_rand_reset.31457398247177906350284960851463375508582332218872532402743634219835757539355
Line 254, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 730732825 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 730732825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.