AON_TIMER Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	564.859us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.910s	889.795us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	491.008us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	15.670s	7.317ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.470s	509.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	526.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	491.008us	20	20	100.00
		aon_timer_csr_aliasing	1.470s	509.807us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.930s	518.295us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.280s	484.926us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.436m	51.992ms	50	50	100.00
V2	jump	aon_timer_jump	1.570s	575.605us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.514m	482.345ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.300s	497.970us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.910s	568.994us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.910s	568.994us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.910s	889.795us	5	5	100.00
		aon_timer_csr_rw	1.380s	491.008us	20	20	100.00
		aon_timer_csr_aliasing	1.470s	509.807us	5	5	100.00
		aon_timer_same_csr_outstanding	7.390s	2.532ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.910s	889.795us	5	5	100.00
		aon_timer_csr_rw	1.380s	491.008us	20	20	100.00
		aon_timer_csr_aliasing	1.470s	509.807us	5	5	100.00
		aon_timer_same_csr_outstanding	7.390s	2.532ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.830s	8.068ms	5	5	100.00
		aon_timer_tl_intg_err	14.610s	8.577ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.610s	8.577ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.727m	416.788ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

2.aon_timer_stress_all_with_rand_reset.87202187831177733982736477898065310017984235473369867685825650833736829063431
Line 574, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48177411081 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 48177411081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.100980775484717864802052290364963442457597525968578528460209217909811189912247
Line 324, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28873453441 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 28873453441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 1 failures.

26.aon_timer_stress_all.2843237077724513316204635891102411926425356804632950486507938914920016431798
Line 292, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 316302309901 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 316302309901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---