AON_TIMER Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	581.616us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.490s	1.368ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	480.400us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.380s	8.027ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.440s	503.070us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.480s	497.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	480.400us	20	20	100.00
		aon_timer_csr_aliasing	1.440s	503.070us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.210s	459.662us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	486.100us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.595m	61.380ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	525.648us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.307m	461.147ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.400s	506.686us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.750s	389.297us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.750s	389.297us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.490s	1.368ms	5	5	100.00
		aon_timer_csr_rw	1.410s	480.400us	20	20	100.00
		aon_timer_csr_aliasing	1.440s	503.070us	5	5	100.00
		aon_timer_same_csr_outstanding	6.790s	2.437ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.490s	1.368ms	5	5	100.00
		aon_timer_csr_rw	1.410s	480.400us	20	20	100.00
		aon_timer_csr_aliasing	1.440s	503.070us	5	5	100.00
		aon_timer_same_csr_outstanding	6.790s	2.437ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	11.740s	7.808ms	5	5	100.00
		aon_timer_tl_intg_err	13.830s	8.658ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.830s	8.658ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.257m	572.141ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

5.aon_timer_stress_all_with_rand_reset.25035057346544318351022481194878399868529439628636018914600553426996397490067
Line 262, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 701918399 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 701918399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.aon_timer_stress_all_with_rand_reset.32761463091456441470077571453030547927348050532599228699720383799443161698753
Line 803, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 158191713417 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 158191713417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 2 failures.

42.aon_timer_stress_all.114976567952408277405210288603592889145783620531445644657858266842835852743304
Line 264, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 190051652032 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 190051652032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.aon_timer_stress_all.97434070469616350559142692260322736721024230783261745806289948010558422774222
Line 264, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 69756725920 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 69756725920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---