AON_TIMER Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.510s	580.220us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.500s	1.194ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.420s	472.317us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.700s	13.125ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.360s	491.443us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.650s	614.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.420s	472.317us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	491.443us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.300s	509.227us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.060s	362.689us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.519m	61.091ms	50	50	100.00
V2	jump	aon_timer_jump	1.530s	549.116us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.465m	471.201ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.330s	494.394us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.460s	753.907us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.460s	753.907us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.500s	1.194ms	5	5	100.00
		aon_timer_csr_rw	1.420s	472.317us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	491.443us	5	5	100.00
		aon_timer_same_csr_outstanding	5.700s	2.097ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.500s	1.194ms	5	5	100.00
		aon_timer_csr_rw	1.420s	472.317us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	491.443us	5	5	100.00
		aon_timer_same_csr_outstanding	5.700s	2.097ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	7.080s	3.976ms	5	5	100.00
		aon_timer_tl_intg_err	14.700s	8.771ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.700s	8.771ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.392m	343.567ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all has 4 failures.

14.aon_timer_stress_all.52923309972064843231441671739782489715062179982453955258969110893073481867893
Line 312, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 188527736895 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 188527736895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.aon_timer_stress_all.100042077502824875774761855488490319585388624014027299103501881477758150793043
Line 275, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 37374640988 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 37374640988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 8 failures.

15.aon_timer_stress_all_with_rand_reset.16444485150144086086054242254342261216588120994005920349464481296440135237884
Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1411210520 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1411210520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aon_timer_stress_all_with_rand_reset.39889387978772100321263782284723244750850915946244165110031809403955264562792
Line 674, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43085760752 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 43085760752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:323) [scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 5.aon_timer_stress_all_with_rand_reset.98914476954714062647644947633333495413146807016601971258497487612368551284928
    Line 1210, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 58436384481 ps: (aon_timer_scoreboard.sv:323) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 58436384481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```