AON_TIMER Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	499.635us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.500s	660.434us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	512.385us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	24.290s	13.939ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.840s	543.836us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.430s	451.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	512.385us	20	20	100.00
		aon_timer_csr_aliasing	1.840s	543.836us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.260s	502.973us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.760s	335.582us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.525m	59.865ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	559.490us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.876m	577.322ms	44	50	88.00
V2	intr_test	aon_timer_intr_test	1.380s	515.649us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.430s	333.405us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.430s	333.405us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.500s	660.434us	5	5	100.00
		aon_timer_csr_rw	1.370s	512.385us	20	20	100.00
		aon_timer_csr_aliasing	1.840s	543.836us	5	5	100.00
		aon_timer_same_csr_outstanding	9.010s	3.431ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.500s	660.434us	5	5	100.00
		aon_timer_csr_rw	1.370s	512.385us	20	20	100.00
		aon_timer_csr_aliasing	1.840s	543.836us	5	5	100.00
		aon_timer_same_csr_outstanding	9.010s	3.431ms	20	20	100.00
V2		TOTAL			234	240	97.50
V2S	tl_intg_err	aon_timer_sec_cm	11.270s	7.390ms	5	5	100.00
		aon_timer_tl_intg_err	15.260s	8.958ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.260s	8.958ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	25.246m	1.049s	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			416	430	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 14 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

0.aon_timer_stress_all_with_rand_reset.82475575441906542606972683237731569541180787499837576327128841804099589494877
Line 334, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22179806450 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 22179806450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.63629558761475609820750310637918288367238879224912078791539364358125934854156
Line 455, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29405406584 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 29405406584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 6 failures.

2.aon_timer_stress_all.108432534498300223572714687279353411550544738540254492697549545520669888444022
Line 315, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 158192109096 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 158192109096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aon_timer_stress_all.36062064942301485507658212277170382361752789462372013461632346806476408646243
Line 274, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 39632380359 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 39632380359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.