AON_TIMER Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.430s	548.115us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.570s	1.334ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.330s	511.438us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.860s	13.990ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.520s	496.052us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	540.141us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.330s	511.438us	20	20	100.00
		aon_timer_csr_aliasing	1.520s	496.052us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.080s	389.610us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.810s	388.945us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.477m	57.372ms	50	50	100.00
V2	jump	aon_timer_jump	1.580s	615.181us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.008m	438.986ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.350s	518.945us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.640s	394.059us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.640s	394.059us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.570s	1.334ms	5	5	100.00
		aon_timer_csr_rw	1.330s	511.438us	20	20	100.00
		aon_timer_csr_aliasing	1.520s	496.052us	5	5	100.00
		aon_timer_same_csr_outstanding	6.300s	2.817ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.570s	1.334ms	5	5	100.00
		aon_timer_csr_rw	1.330s	511.438us	20	20	100.00
		aon_timer_csr_aliasing	1.520s	496.052us	5	5	100.00
		aon_timer_same_csr_outstanding	6.300s	2.817ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	6.950s	4.196ms	5	5	100.00
		aon_timer_tl_intg_err	13.980s	7.886ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.980s	7.886ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.816m	112.182ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

1.aon_timer_stress_all_with_rand_reset.85379859600612839856650746463532497113438117572260518160328253895683993245117
Line 609, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 135736693758 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 135736693758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.aon_timer_stress_all_with_rand_reset.28840241696993897518879563805932782592401250190709718659679332516078082266798
Line 412, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15274654055 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 15274654055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 4 failures.

7.aon_timer_stress_all.58805604762186943049072699445483080798411839958146523631203986186397553007010
Line 276, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 2158757090 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2158757090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.aon_timer_stress_all.45556031162423201490460391843374376355363320284292842906413009438196426542935
Line 311, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 157074131425 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 157074131425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.