AON_TIMER Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.600s	612.956us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.360s	1.271ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.300s	539.982us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	17.880s	6.306ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.340s	400.755us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	605.778us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.300s	539.982us	20	20	100.00
		aon_timer_csr_aliasing	1.340s	400.755us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.100s	389.557us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.910s	303.894us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.625m	59.473ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	573.893us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.247m	334.603ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.310s	483.587us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.750s	409.951us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.750s	409.951us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.360s	1.271ms	5	5	100.00
		aon_timer_csr_rw	1.300s	539.982us	20	20	100.00
		aon_timer_csr_aliasing	1.340s	400.755us	5	5	100.00
		aon_timer_same_csr_outstanding	5.050s	1.818ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.360s	1.271ms	5	5	100.00
		aon_timer_csr_rw	1.300s	539.982us	20	20	100.00
		aon_timer_csr_aliasing	1.340s	400.755us	5	5	100.00
		aon_timer_same_csr_outstanding	5.050s	1.818ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	14.280s	8.291ms	5	5	100.00
		aon_timer_tl_intg_err	14.030s	8.309ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.030s	8.309ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.408m	93.819ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 6 failures:

Test aon_timer_stress_all has 1 failures.

1.aon_timer_stress_all.24518465534150671625103270323079720049760639920284368650753704732583973485439
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 89100767124 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 89100767124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 5 failures.

2.aon_timer_stress_all_with_rand_reset.59371395068683381108741173767350698241578471495206093637440971889262347286443
Line 647, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43777720908 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 43777720908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aon_timer_stress_all_with_rand_reset.69638170811233481527425689673086331160857797319731273254661377227967092051890
Line 828, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 63657804422 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 63657804422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.