AON_TIMER Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.430s	580.826us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.330s	1.145ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.310s	452.814us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.320s	12.047ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.570s	606.298us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.650s	614.747us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.310s	452.814us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	606.298us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.960s	273.015us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.120s	442.208us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	51.780s	31.263ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	577.799us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.530m	362.491ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.300s	465.816us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.700s	351.245us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.700s	351.245us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.330s	1.145ms	5	5	100.00
		aon_timer_csr_rw	1.310s	452.814us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	606.298us	5	5	100.00
		aon_timer_same_csr_outstanding	4.900s	2.796ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.330s	1.145ms	5	5	100.00
		aon_timer_csr_rw	1.310s	452.814us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	606.298us	5	5	100.00
		aon_timer_same_csr_outstanding	4.900s	2.796ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	14.200s	7.477ms	5	5	100.00
		aon_timer_tl_intg_err	14.160s	8.288ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.160s	8.288ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.800m	756.725ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 9 failures.

3.aon_timer_stress_all_with_rand_reset.49389250637044314080540784547578312505969414129326741739814683448473727648962
Line 1338, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 767758172368 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 767758172368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all_with_rand_reset.55233758342346817484481949159958749068420565394471762115842029740303428198380
Line 823, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 49786965169 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 49786965169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aon_timer_stress_all has 1 failures.

27.aon_timer_stress_all.48087190001120775002077923055228735530028407401347546965582431144797084397115
Line 310, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 124644041978 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 124644041978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---