AON_TIMER Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.560s	438.679us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.890s	1.006ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.880s	528.413us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	27.640s	13.881ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.690s	435.620us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.790s	544.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.880s	528.413us	20	20	100.00
		aon_timer_csr_aliasing	2.690s	435.620us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.560s	452.444us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.240s	410.571us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.607m	32.839ms	50	50	100.00
V2	jump	aon_timer_jump	2.840s	611.853us	50	50	100.00
V2	stress_all	aon_timer_stress_all	17.176m	506.046ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	2.510s	510.317us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.630s	584.086us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.630s	584.086us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.890s	1.006ms	5	5	100.00
		aon_timer_csr_rw	2.880s	528.413us	20	20	100.00
		aon_timer_csr_aliasing	2.690s	435.620us	5	5	100.00
		aon_timer_same_csr_outstanding	10.220s	2.150ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.890s	1.006ms	5	5	100.00
		aon_timer_csr_rw	2.880s	528.413us	20	20	100.00
		aon_timer_csr_aliasing	2.690s	435.620us	5	5	100.00
		aon_timer_same_csr_outstanding	10.220s	2.150ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	20.230s	7.296ms	5	5	100.00
		aon_timer_tl_intg_err	26.950s	8.181ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	26.950s	8.181ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.233m	57.409ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.79	99.32	95.61	100.00	--	98.38	99.51	45.90

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 6 failures:

Test aon_timer_stress_all has 4 failures.

5.aon_timer_stress_all.29353682652030177018174785859150081061559743024867560365445456507886217102350
Line 94, in log /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 53507292931 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 53507292931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.aon_timer_stress_all.27582934150217560492783786256293990990338246048945663828223359074672031710319
Line 122, in log /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 47903648300 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 47903648300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 2 failures.

13.aon_timer_stress_all_with_rand_reset.98365892729780924751959580996255864416886951323048346564609018227218717822599
Line 186, in log /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8024179513 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 8024179513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aon_timer_stress_all_with_rand_reset.88845736930257460722937914232985048671104888943508769529368376549356217574550
Line 147, in log /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1472184936 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1472184936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---