AON_TIMER Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.390s	513.135us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.500s	920.123us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.640s	559.063us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	6.300s	13.485ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.730s	527.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.960s	575.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.640s	559.063us	20	20	100.00
		aon_timer_csr_aliasing	1.730s	527.251us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.680s	492.158us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.560s	479.863us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.941m	49.235ms	50	50	100.00
V2	jump	aon_timer_jump	2.930s	604.205us	50	50	100.00
V2	stress_all	aon_timer_stress_all	20.340m	610.034ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.580s	450.292us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.100s	446.103us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.100s	446.103us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.500s	920.123us	5	5	100.00
		aon_timer_csr_rw	1.640s	559.063us	20	20	100.00
		aon_timer_csr_aliasing	1.730s	527.251us	5	5	100.00
		aon_timer_same_csr_outstanding	8.700s	2.924ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.500s	920.123us	5	5	100.00
		aon_timer_csr_rw	1.640s	559.063us	20	20	100.00
		aon_timer_csr_aliasing	1.730s	527.251us	5	5	100.00
		aon_timer_same_csr_outstanding	8.700s	2.924ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	8.320s	4.071ms	5	5	100.00
		aon_timer_tl_intg_err	16.670s	8.724ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	16.670s	8.724ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	50.940s	18.305ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.40	99.32	95.61	100.00	--	98.38	99.51	43.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all has 2 failures.

25.aon_timer_stress_all.96527828513424745948831310033439446714535955993487757064252643530001010564613
Line 122, in log /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/25.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 275216540178 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 275216540178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aon_timer_stress_all.17121000792897574030349715315045182986931222597276266199822654486932731998217
Line 98, in log /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/37.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 14210127363 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 14210127363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 3 failures.

33.aon_timer_stress_all_with_rand_reset.43013443541251791460497988264047869420823496671087852715833119613886617577321
Line 175, in log /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7572451249 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7572451249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.aon_timer_stress_all_with_rand_reset.105353003101881788368006980983355810548189968753281223181472528812975862745090
Line 100, in log /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4450720251 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4450720251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:771) [aon_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 46.aon_timer_stress_all_with_rand_reset.5771295349338711260008485433353215747282261639145591994102396781586041447109
    Line 179, in log /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2042487567 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2042487567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```