AON_TIMER Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.510s	555.652us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.240s	1.191ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.870s	399.837us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.960s	13.970ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.200s	525.386us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.220s	499.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.870s	399.837us	20	20	100.00
		aon_timer_csr_aliasing	2.200s	525.386us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.570s	463.244us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.780s	430.400us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	2.974m	59.439ms	50	50	100.00
V2	jump	aon_timer_jump	2.690s	605.467us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.172m	433.917ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	2.220s	426.589us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.330s	483.353us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.330s	483.353us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.240s	1.191ms	5	5	100.00
		aon_timer_csr_rw	1.870s	399.837us	20	20	100.00
		aon_timer_csr_aliasing	2.200s	525.386us	5	5	100.00
		aon_timer_same_csr_outstanding	7.830s	2.852ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.240s	1.191ms	5	5	100.00
		aon_timer_csr_rw	1.870s	399.837us	20	20	100.00
		aon_timer_csr_aliasing	2.200s	525.386us	5	5	100.00
		aon_timer_same_csr_outstanding	7.830s	2.852ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	23.570s	7.779ms	5	5	100.00
		aon_timer_tl_intg_err	14.390s	7.755ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.390s	7.755ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.260m	9.204ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.16	99.33	95.61	100.00	--	98.40	99.51	42.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

1.aon_timer_stress_all_with_rand_reset.7411748320812401345614255762343441362392421087122512445561902196905259396768
Line 142, in log /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1963807856 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1963807856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aon_timer_stress_all_with_rand_reset.103189660317326071888473840538595543427548239943949754490926733442074803683738
Line 177, in log /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2365225368 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2365225368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 1 failures.

21.aon_timer_stress_all.39147707354907050390034672607701499197365083602747341304081207969533852698732
Line 126, in log /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/21.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 229808805268 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 229808805268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---