AON_TIMER Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.870s	575.879us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	4.160s	1.086ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.640s	519.046us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	30.230s	13.022ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	3.800s	645.412us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.250s	376.612us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.640s	519.046us	20	20	100.00
		aon_timer_csr_aliasing	3.800s	645.412us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.650s	457.330us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.900s	336.617us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	2.355m	55.660ms	50	50	100.00
V2	jump	aon_timer_jump	2.930s	591.803us	50	50	100.00
V2	stress_all	aon_timer_stress_all	19.083m	624.093ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	2.630s	510.753us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.670s	571.833us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.670s	571.833us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	4.160s	1.086ms	5	5	100.00
		aon_timer_csr_rw	2.640s	519.046us	20	20	100.00
		aon_timer_csr_aliasing	3.800s	645.412us	5	5	100.00
		aon_timer_same_csr_outstanding	11.770s	2.877ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	4.160s	1.086ms	5	5	100.00
		aon_timer_csr_rw	2.640s	519.046us	20	20	100.00
		aon_timer_csr_aliasing	3.800s	645.412us	5	5	100.00
		aon_timer_same_csr_outstanding	11.770s	2.877ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	13.570s	7.762ms	5	5	100.00
		aon_timer_tl_intg_err	19.970s	7.534ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	19.970s	7.534ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.415m	26.689ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.31	99.32	95.61	100.00	--	98.38	99.51	43.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

2.aon_timer_stress_all_with_rand_reset.75818570164921570964142704047461946313023375105005374335029126878421088219370
Line 246, in log /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3328600650 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3328600650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all_with_rand_reset.23380498377514890187593667954606955143180956890639077214524682379634454546275
Line 236, in log /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11536110194 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 11536110194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 4 failures.

12.aon_timer_stress_all.55840367771906858638697495155266102732500540681896028666707213186066953173675
Line 98, in log /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 128133723989 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 128133723989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all.7972816418111321779462486715423288580577289076927396861928500210432534260192
Line 110, in log /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/23.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 95653312975 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 95653312975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.