7e34e67ade| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 2.800s | 594.452us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 3.160s | 1.390ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 2.470s | 467.435us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 25.090s | 5.217ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 2.800s | 577.445us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 2.100s | 353.641us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 2.470s | 467.435us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 2.800s | 577.445us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 2.110s | 451.076us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.960s | 471.892us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.963m | 52.610ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 2.700s | 513.044us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 23.723m | 849.673ms | 49 | 50 | 98.00 |
| V2 | intr_test | aon_timer_intr_test | 2.260s | 458.941us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.760s | 791.292us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.760s | 791.292us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 3.160s | 1.390ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 2.470s | 467.435us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 2.800s | 577.445us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 10.830s | 2.627ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 3.160s | 1.390ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 2.470s | 467.435us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 2.800s | 577.445us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 10.830s | 2.627ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 239 | 240 | 99.58 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 20.690s | 8.157ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 19.080s | 8.701ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 19.080s | 8.701ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 1.097m | 76.079ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 423 | 430 | 98.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.58 | 99.32 | 95.61 | 100.00 | -- | 98.38 | 99.51 | 44.64 |
UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 6 failures:
8.aon_timer_stress_all_with_rand_reset.19758880434381645296855024365792066156761530314008526496425963853413526528296
Line 285, in log /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3141689109 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 3141689109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.aon_timer_stress_all_with_rand_reset.42814252043293899136289598106297736539997916679046624462446306127041546535459
Line 80, in log /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 689216895 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 689216895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (aon_timer_scoreboard.sv:426) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
26.aon_timer_stress_all.78425178018545193077294282159449690795143706277118937367506411720732574228636
Line 91, in log /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log
UVM_ERROR @ 2148970765 ps: (aon_timer_scoreboard.sv:426) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2148970765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---