AON_TIMER Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.820s	576.726us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.570s	1.097ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.480s	436.456us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	11.780s	7.159ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.850s	599.235us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.640s	418.886us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.480s	436.456us	20	20	100.00
		aon_timer_csr_aliasing	1.850s	599.235us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.320s	489.995us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.120s	380.362us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.573m	56.099ms	50	50	100.00
V2	jump	aon_timer_jump	2.680s	535.550us	50	50	100.00
V2	stress_all	aon_timer_stress_all	16.824m	545.812ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.390s	475.056us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.060s	487.645us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.060s	487.645us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.570s	1.097ms	5	5	100.00
		aon_timer_csr_rw	1.480s	436.456us	20	20	100.00
		aon_timer_csr_aliasing	1.850s	599.235us	5	5	100.00
		aon_timer_same_csr_outstanding	8.620s	2.353ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.570s	1.097ms	5	5	100.00
		aon_timer_csr_rw	1.480s	436.456us	20	20	100.00
		aon_timer_csr_aliasing	1.850s	599.235us	5	5	100.00
		aon_timer_same_csr_outstanding	8.620s	2.353ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	22.900s	7.905ms	5	5	100.00
		aon_timer_tl_intg_err	15.480s	8.499ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.480s	8.499ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	52.610s	17.846ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			427	430	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.81	99.32	95.61	100.00	--	98.38	99.51	46.03

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 3 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

0.aon_timer_stress_all_with_rand_reset.51711561236619216585753915259461135018630996694743258362494110065421441968586
Line 114, in log /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 923560628 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 923560628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.aon_timer_stress_all_with_rand_reset.90763568464627549018566404020318430980718269601520007046127111906744408203761
Line 101, in log /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2867187945 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2867187945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 1 failures.

17.aon_timer_stress_all.70743527492791393317728603095712812131758605486010070887207501418305219743627
Line 106, in log /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 3317231628 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3317231628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---