V1 |
smoke |
clkmgr_smoke |
1.410s |
239.966us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
clkmgr_csr_hw_reset |
0.920s |
33.419us |
5 |
5 |
100.00 |
V1 |
csr_rw |
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
clkmgr_csr_bit_bash |
11.630s |
1.992ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
clkmgr_csr_aliasing |
1.600s |
106.004us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
clkmgr_csr_mem_rw_with_rand_reset |
1.740s |
218.251us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
1.600s |
106.004us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
peri_enables |
clkmgr_peri |
0.950s |
93.586us |
50 |
50 |
100.00 |
V2 |
trans_enables |
clkmgr_trans |
1.680s |
272.486us |
50 |
50 |
100.00 |
V2 |
extclk |
clkmgr_extclk |
1.370s |
251.107us |
50 |
50 |
100.00 |
V2 |
clk_status |
clkmgr_clk_status |
1.140s |
225.742us |
50 |
50 |
100.00 |
V2 |
jitter |
clkmgr_smoke |
1.410s |
239.966us |
50 |
50 |
100.00 |
V2 |
frequency |
clkmgr_frequency |
17.460s |
2.364ms |
50 |
50 |
100.00 |
V2 |
frequency_timeout |
clkmgr_frequency_timeout |
17.240s |
2.419ms |
50 |
50 |
100.00 |
V2 |
frequency_overflow |
clkmgr_frequency |
17.460s |
2.364ms |
50 |
50 |
100.00 |
V2 |
stress_all |
clkmgr_stress_all |
1.142m |
10.465ms |
50 |
50 |
100.00 |
V2 |
intr_test |
clkmgr_intr_test |
0.940s |
154.159us |
50 |
50 |
100.00 |
V2 |
alert_test |
clkmgr_alert_test |
1.030s |
120.071us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
clkmgr_tl_errors |
4.780s |
464.401us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
clkmgr_tl_errors |
4.780s |
464.401us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
clkmgr_csr_hw_reset |
0.920s |
33.419us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
1.600s |
106.004us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
2.020s |
306.439us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
clkmgr_csr_hw_reset |
0.920s |
33.419us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
1.600s |
106.004us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
2.020s |
306.439us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
490 |
490 |
100.00 |
V2S |
tl_intg_err |
clkmgr_sec_cm |
3.470s |
460.273us |
5 |
5 |
100.00 |
|
|
clkmgr_tl_intg_err |
6.660s |
1.749ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error |
clkmgr_shadow_reg_errors |
4.350s |
1.126ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_read_clear_staged_value |
clkmgr_shadow_reg_errors |
4.350s |
1.126ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_storage_error |
clkmgr_shadow_reg_errors |
4.350s |
1.126ms |
20 |
20 |
100.00 |
V2S |
shadowed_reset_glitch |
clkmgr_shadow_reg_errors |
4.350s |
1.126ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error_with_csr_rw |
clkmgr_shadow_reg_errors_with_csr_rw |
7.640s |
2.234ms |
20 |
20 |
100.00 |
V2S |
sec_cm_bus_integrity |
clkmgr_tl_intg_err |
6.660s |
1.749ms |
20 |
20 |
100.00 |
V2S |
sec_cm_meas_clk_bkgn_chk |
clkmgr_frequency |
17.460s |
2.364ms |
50 |
50 |
100.00 |
V2S |
sec_cm_timeout_clk_bkgn_chk |
clkmgr_frequency_timeout |
17.240s |
2.419ms |
50 |
50 |
100.00 |
V2S |
sec_cm_meas_config_shadow |
clkmgr_shadow_reg_errors |
4.350s |
1.126ms |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_intersig_mubi |
clkmgr_idle_intersig_mubi |
1.890s |
347.402us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_intersig_mubi |
clkmgr_lc_ctrl_intersig_mubi |
1.340s |
206.665us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_clk_handshake_intersig_mubi |
clkmgr_lc_clk_byp_req_intersig_mubi |
1.490s |
290.981us |
50 |
50 |
100.00 |
V2S |
sec_cm_clk_handshake_intersig_mubi |
clkmgr_clk_handshake_intersig_mubi |
1.260s |
163.799us |
50 |
50 |
100.00 |
V2S |
sec_cm_div_intersig_mubi |
clkmgr_div_intersig_mubi |
1.390s |
230.320us |
50 |
50 |
100.00 |
V2S |
sec_cm_jitter_config_mubi |
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_ctr_redun |
clkmgr_sec_cm |
3.470s |
460.273us |
5 |
5 |
100.00 |
V2S |
sec_cm_meas_config_regwen |
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
V2S |
sec_cm_clk_ctrl_config_regwen |
clkmgr_csr_rw |
1.370s |
291.213us |
20 |
20 |
100.00 |
V2S |
prim_count_check |
clkmgr_sec_cm |
3.470s |
460.273us |
5 |
5 |
100.00 |
V2S |
|
TOTAL |
|
|
315 |
315 |
100.00 |
V3 |
stress_all_with_rand_reset |
clkmgr_stress_all_with_rand_reset |
23.258m |
214.389ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
960 |
960 |
100.00 |