CLKMGR Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.520s	219.811us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	61.852us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	6.370s	410.698us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.780s	66.063us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.760s	95.328us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
		clkmgr_csr_aliasing	1.780s	66.063us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.210s	184.113us	49	50	98.00
V2	trans_enables	clkmgr_trans	1.990s	405.911us	50	50	100.00
V2	extclk	clkmgr_extclk	1.440s	226.143us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.250s	238.709us	50	50	100.00
V2	jitter	clkmgr_smoke	1.520s	219.811us	50	50	100.00
V2	frequency	clkmgr_frequency	18.340s	2.363ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.180s	2.059ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.340s	2.363ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	2.316m	18.888ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	130.736us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.190s	150.401us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.290s	1.319ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.290s	1.319ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	61.852us	5	5	100.00
		clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
		clkmgr_csr_aliasing	1.780s	66.063us	5	5	100.00
		clkmgr_same_csr_outstanding	2.740s	553.850us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	61.852us	5	5	100.00
		clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
		clkmgr_csr_aliasing	1.780s	66.063us	5	5	100.00
		clkmgr_same_csr_outstanding	2.740s	553.850us	20	20	100.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	clkmgr_sec_cm	3.840s	650.220us	5	5	100.00
		clkmgr_tl_intg_err	6.160s	1.745ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.360s	705.842us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.360s	705.842us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.360s	705.842us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.360s	705.842us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.280s	706.059us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	6.160s	1.745ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.340s	2.363ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.180s	2.059ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.360s	705.842us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.740s	260.616us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.900s	394.979us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.360s	179.275us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.720s	270.257us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.830s	334.936us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.840s	650.220us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.910s	17.100us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.840s	650.220us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.210s	1.276ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	26.649m	333.066ms	47	50	94.00
V3		TOTAL			97	100	97.00
		TOTAL			1006	1010	99.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 2 failures:

  • Test clkmgr_stress_all_with_rand_reset has 2 failures.

    • 3.clkmgr_stress_all_with_rand_reset.50751075307298113020478153082297475424356132615925676983665554279660101808943
      Line 497, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 9936366709 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 9936366709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 27.clkmgr_stress_all_with_rand_reset.76406520014984732450629413418079795471650604317052599023713630226580217648753
      Line 293, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 2813207554 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 2813207554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 2 failures:

  • Test clkmgr_peri has 1 failures.

    • 13.clkmgr_peri.114405986492058685675734293651141767388798830039871632795508352624288824903750
      Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_peri/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @   2783927 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @   2783927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 14.clkmgr_stress_all_with_rand_reset.45966483293843262978199031054940476166920511429936588588027425332705674411490
      Line 619, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 5247616037 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 5247616037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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