CLKMGR Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.810s	356.447us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.980s	65.737us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	13.130s	2.374ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.190s	226.999us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.910s	30.640us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
		clkmgr_csr_aliasing	2.190s	226.999us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.140s	150.587us	49	50	98.00
V2	trans_enables	clkmgr_trans	2.300s	478.166us	50	50	100.00
V2	extclk	clkmgr_extclk	1.370s	200.695us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.960s	104.807us	50	50	100.00
V2	jitter	clkmgr_smoke	1.810s	356.447us	50	50	100.00
V2	frequency	clkmgr_frequency	18.140s	2.360ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.360s	2.423ms	49	50	98.00
V2	frequency_overflow	clkmgr_frequency	18.140s	2.360ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.344m	11.970ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.970s	112.443us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.180s	159.284us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.360s	1.166ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.360s	1.166ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.980s	65.737us	5	5	100.00
		clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
		clkmgr_csr_aliasing	2.190s	226.999us	5	5	100.00
		clkmgr_same_csr_outstanding	1.970s	419.588us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.980s	65.737us	5	5	100.00
		clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
		clkmgr_csr_aliasing	2.190s	226.999us	5	5	100.00
		clkmgr_same_csr_outstanding	1.970s	419.588us	20	20	100.00
V2		TOTAL			488	490	99.59
V2S	tl_intg_err	clkmgr_sec_cm	3.600s	475.704us	5	5	100.00
		clkmgr_tl_intg_err	4.640s	596.038us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.290s	582.749us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.290s	582.749us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.290s	582.749us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.290s	582.749us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.110s	765.959us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.640s	596.038us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.140s	2.360ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.360s	2.423ms	49	50	98.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.290s	582.749us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.640s	306.327us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.690s	323.181us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.350s	187.912us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	2.150s	451.283us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.610s	307.281us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.600s	475.704us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.080s	136.118us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.600s	475.704us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.780s	1.404ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	20.976m	221.428ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:

  • Test clkmgr_peri has 1 failures.

    • 10.clkmgr_peri.64717420053630011124863235485292594421645705921393806258002089130410314025799
      Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_peri/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @   2870747 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @   2870747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job clkmgr-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test clkmgr_frequency_timeout has 1 failures.

    • 12.clkmgr_frequency_timeout.19375331963392029972374260243865920148541234094291306072362225118308787856293
      Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest/run.log

        Job ID: smart:ee3c74c6-1b99-4810-be1a-b3cf2ae54dc7
      

Past Results

• Latest
• lint
• 2024.01.18_08.26.44
• 2024.01.15_03.44.36
• 2024.01.11_02.59.35
• 2024.01.08_02.46.46
• 2024.01.04_01.10.51
• 2024.01.01_00.38.30