4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | peri_enables | clkmgr_peri | 0 | 50 | 0.00 | ||
| V2 | trans_enables | clkmgr_trans | 0 | 50 | 0.00 | ||
| V2 | extclk | clkmgr_extclk | 0 | 50 | 0.00 | ||
| V2 | clk_status | clkmgr_clk_status | 0 | 50 | 0.00 | ||
| V2 | jitter | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V2 | frequency | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | frequency_timeout | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2 | frequency_overflow | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | stress_all | clkmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | clkmgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | clkmgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 490 | 0.00 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | prim_count_check | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 315 | 0.00 | |||
| V3 | regwen | clkmgr_regwen | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 0 | 1010 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1012 failures:
0.clkmgr_smoke.105365851147084140815762068944641437430118716397585635207169813713377617027871
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_smoke/latest/run.log
1.clkmgr_smoke.3188671808434614274507648924642368418717693366110979867927584279374354112659
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_smoke/latest/run.log
... and 48 more failures.
0.clkmgr_extclk.79352034711976275150731504726601374000321480787374199381226988284563262812096
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_extclk/latest/run.log
1.clkmgr_extclk.110712440338677448491414700108217875035266763227559308300252898437701777680762
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_extclk/latest/run.log
... and 48 more failures.
0.clkmgr_frequency.31394735163175308524148976512970880994307675976043754654837251951066361051950
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log
1.clkmgr_frequency.44686095813094335962778421995646306873744092495693765019930059093354075705052
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log
... and 48 more failures.
0.clkmgr_frequency_timeout.41798900874318633922330631624164936901990348396351883232152123622561641880552
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log
1.clkmgr_frequency_timeout.4247870173254870573854004002769273756445460733138208682480181246099233024635
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log
... and 48 more failures.
0.clkmgr_peri.107432524772051459095973897431888370152437835845437747001154257378534091677911
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_peri/latest/run.log
1.clkmgr_peri.58841139568665057953172517931549080805316282079884518849643101031170374896164
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_peri/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.