CLKMGR Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.310s	203.794us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.860s	39.251us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.210s	1.416ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.270s	344.457us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.890s	58.451us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
		clkmgr_csr_aliasing	2.270s	344.457us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.250s	191.900us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.120s	409.459us	50	50	100.00
V2	extclk	clkmgr_extclk	1.550s	290.540us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.950s	111.533us	50	50	100.00
V2	jitter	clkmgr_smoke	1.310s	203.794us	50	50	100.00
V2	frequency	clkmgr_frequency	17.670s	2.356ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.300s	2.181ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.670s	2.356ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.573m	12.735ms	49	50	98.00
V2	intr_test	clkmgr_intr_test	0.790s	73.016us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.170s	149.507us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.580s	1.006ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.580s	1.006ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.860s	39.251us	5	5	100.00
		clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
		clkmgr_csr_aliasing	2.270s	344.457us	5	5	100.00
		clkmgr_same_csr_outstanding	1.590s	177.018us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.860s	39.251us	5	5	100.00
		clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
		clkmgr_csr_aliasing	2.270s	344.457us	5	5	100.00
		clkmgr_same_csr_outstanding	1.590s	177.018us	20	20	100.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	clkmgr_sec_cm	12.460s	2.667ms	5	5	100.00
		clkmgr_tl_intg_err	4.030s	672.247us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.880s	511.678us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.880s	511.678us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.880s	511.678us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.880s	511.678us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.770s	937.106us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.030s	672.247us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.670s	2.356ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.300s	2.181ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.880s	511.678us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.650s	264.383us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.630s	305.067us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.610s	280.243us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.420s	210.477us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.170s	101.979us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	12.460s	2.667ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.100s	134.298us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	12.460s	2.667ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.710s	1.139ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	32.263m	515.879ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 2 failures:

  • Test clkmgr_stress_all has 1 failures.

    • 10.clkmgr_stress_all.91871153314032505681084593459981853988652734463909997037116892025388578536731
      Line 272, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_stress_all/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 887906915 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 887906915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 16.clkmgr_stress_all_with_rand_reset.65608383833421523681175281962031936830542264177922519455439344405942545661142
      Line 1065, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 21769009686 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 21769009686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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