CLKMGR Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.050s	36.620us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.960s	68.461us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.800s	1.333ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.810s	87.988us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.940s	104.044us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
		clkmgr_csr_aliasing	1.810s	87.988us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.160s	169.646us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.150s	458.617us	50	50	100.00
V2	extclk	clkmgr_extclk	1.370s	198.823us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.900s	100.960us	50	50	100.00
V2	jitter	clkmgr_smoke	1.050s	36.620us	50	50	100.00
V2	frequency	clkmgr_frequency	18.620s	2.363ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.120s	2.302ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.620s	2.363ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.358m	10.886ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.860s	99.846us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.220s	138.391us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.010s	268.578us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.010s	268.578us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.960s	68.461us	5	5	100.00
		clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
		clkmgr_csr_aliasing	1.810s	87.988us	5	5	100.00
		clkmgr_same_csr_outstanding	2.110s	369.729us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.960s	68.461us	5	5	100.00
		clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
		clkmgr_csr_aliasing	1.810s	87.988us	5	5	100.00
		clkmgr_same_csr_outstanding	2.110s	369.729us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.850s	971.997us	5	5	100.00
		clkmgr_tl_intg_err	4.710s	1.005ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.260s	167.891us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.260s	167.891us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.260s	167.891us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.260s	167.891us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.360s	1.174ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.710s	1.005ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.620s	2.363ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.120s	2.302ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.260s	167.891us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.120s	461.967us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.920s	399.237us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.240s	158.315us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.620s	219.272us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.860s	306.876us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.850s	971.997us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.310s	238.521us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.850s	971.997us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.750s	1.330ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	43.538m	753.039ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 2 failures:
  • Test clkmgr_stress_all_with_rand_reset has 2 failures.

    • 6.clkmgr_stress_all_with_rand_reset.60464000779672614197844806786840640770918984155195982111387585845838352160095
      Line 734, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 12924428944 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 12924428944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 26.clkmgr_stress_all_with_rand_reset.52986817044436817309138214054453253695147645482840517122908569730611443578543
      Line 413, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 6975207075 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 6975207075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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