93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | peri_enables | clkmgr_peri | 0 | 50 | 0.00 | ||
| V2 | trans_enables | clkmgr_trans | 0 | 50 | 0.00 | ||
| V2 | extclk | clkmgr_extclk | 0 | 50 | 0.00 | ||
| V2 | clk_status | clkmgr_clk_status | 0 | 50 | 0.00 | ||
| V2 | jitter | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V2 | frequency | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | frequency_timeout | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2 | frequency_overflow | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | stress_all | clkmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | clkmgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | clkmgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 490 | 0.00 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | prim_count_check | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 315 | 0.00 | |||
| V3 | regwen | clkmgr_regwen | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 0 | 1010 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1012 failures:
0.clkmgr_smoke.112693479117680933037069307798232091686301384236676370892681017298603262056524
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_smoke/latest/run.log
1.clkmgr_smoke.6229293786157532307312133509670618337020121605903013788336094342207419084177
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_smoke/latest/run.log
... and 48 more failures.
0.clkmgr_extclk.97238115528644610885471182096672174623151600552164188723068636557506826187071
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_extclk/latest/run.log
1.clkmgr_extclk.47431232718655018735697969361788226050825432327769615484404519434967649061413
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_extclk/latest/run.log
... and 48 more failures.
0.clkmgr_frequency.41056419646146847648891546984964825839458496551085857862316049730587196629542
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log
1.clkmgr_frequency.100410718909559457764811170645531420892275460291781053949698818082103267674764
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log
... and 48 more failures.
0.clkmgr_frequency_timeout.28611513214445336141017434432770767355862387637999181537138587336409830655982
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log
1.clkmgr_frequency_timeout.85182002566270968369607920106546729403519067345938960161013146026802977896859
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log
... and 48 more failures.
0.clkmgr_peri.95298056210206785139327068585999292394018161895261258874960114998067124646490
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_peri/latest/run.log
1.clkmgr_peri.58668576937478024130051850399142623180039695829499011548141703797120229973888
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_peri/latest/run.log
... and 48 more failures.
Job clkmgr-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/default/build.log
Job ID: smart:d14f246b-34b5-48f6-99f5-35b6414389da
Job clkmgr-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/build.log
Job ID: smart:586f28fa-3e8c-4d83-9a1e-3a524a43dc94