CLKMGR Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.060s	104.999us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.060s	107.683us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	14.470s	2.779ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.790s	70.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	6.100s	1.052ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
		clkmgr_csr_aliasing	1.790s	70.251us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.190s	177.028us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.310s	537.374us	50	50	100.00
V2	extclk	clkmgr_extclk	1.770s	321.547us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.020s	142.323us	50	50	100.00
V2	jitter	clkmgr_smoke	1.060s	104.999us	50	50	100.00
V2	frequency	clkmgr_frequency	18.770s	2.360ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.080s	2.175ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.770s	2.360ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.575m	13.691ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	117.315us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.220s	171.896us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.850s	807.601us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.850s	807.601us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.060s	107.683us	5	5	100.00
		clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
		clkmgr_csr_aliasing	1.790s	70.251us	5	5	100.00
		clkmgr_same_csr_outstanding	2.410s	285.828us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.060s	107.683us	5	5	100.00
		clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
		clkmgr_csr_aliasing	1.790s	70.251us	5	5	100.00
		clkmgr_same_csr_outstanding	2.410s	285.828us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.810s	620.051us	5	5	100.00
		clkmgr_tl_intg_err	3.730s	622.917us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.100s	571.100us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.100s	571.100us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.100s	571.100us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.100s	571.100us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.890s	448.026us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.730s	622.917us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.770s	2.360ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.080s	2.175ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.100s	571.100us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.950s	431.060us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.390s	204.228us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.720s	343.264us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.460s	233.221us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.240s	140.249us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.810s	620.051us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.010s	83.884us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.810s	620.051us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.330s	1.193ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	25.202m	290.782ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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