CLKMGR Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.100s	125.546us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.910s	40.627us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	14.530s	3.165ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	4.710s	1.366ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.170s	352.690us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
		clkmgr_csr_aliasing	4.710s	1.366ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.180s	170.298us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.470s	159.245us	50	50	100.00
V2	extclk	clkmgr_extclk	1.390s	205.600us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.950s	71.579us	50	50	100.00
V2	jitter	clkmgr_smoke	1.100s	125.546us	50	50	100.00
V2	frequency	clkmgr_frequency	16.760s	2.240ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.600s	2.417ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.760s	2.240ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.194m	9.340ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	108.361us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.060s	89.172us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.980s	546.375us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.980s	546.375us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.910s	40.627us	5	5	100.00
		clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
		clkmgr_csr_aliasing	4.710s	1.366ms	5	5	100.00
		clkmgr_same_csr_outstanding	1.990s	386.482us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.910s	40.627us	5	5	100.00
		clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
		clkmgr_csr_aliasing	4.710s	1.366ms	5	5	100.00
		clkmgr_same_csr_outstanding	1.990s	386.482us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	14.580s	3.321ms	5	5	100.00
		clkmgr_tl_intg_err	4.450s	877.865us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.260s	838.514us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.260s	838.514us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.260s	838.514us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.260s	838.514us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	7.210s	2.060ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.450s	877.865us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.760s	2.240ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.600s	2.417ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.260s	838.514us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.070s	409.855us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.480s	250.483us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.110s	113.825us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.460s	256.014us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.660s	317.125us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	14.580s	3.321ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.030s	129.566us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	14.580s	3.321ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.840s	1.100ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	41.444m	737.866ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	99.11	95.67	100.00	100.00	98.71	97.01	98.80

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