CLKMGR Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.670s	318.553us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	103.939us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	14.170s	3.171ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.760s	520.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.060s	365.873us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
		clkmgr_csr_aliasing	2.760s	520.807us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.090s	148.975us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.390s	193.736us	50	50	100.00
V2	extclk	clkmgr_extclk	1.240s	127.634us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.990s	130.118us	50	50	100.00
V2	jitter	clkmgr_smoke	1.670s	318.553us	50	50	100.00
V2	frequency	clkmgr_frequency	18.630s	2.479ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.120s	2.415ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.630s	2.479ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.312m	15.225ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.770s	11.833us	50	50	100.00
V2	alert_test	clkmgr_alert_test	0.910s	54.313us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.550s	457.803us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.550s	457.803us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	103.939us	5	5	100.00
		clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
		clkmgr_csr_aliasing	2.760s	520.807us	5	5	100.00
		clkmgr_same_csr_outstanding	1.950s	297.939us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	103.939us	5	5	100.00
		clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
		clkmgr_csr_aliasing	2.760s	520.807us	5	5	100.00
		clkmgr_same_csr_outstanding	1.950s	297.939us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	6.020s	1.160ms	5	5	100.00
		clkmgr_tl_intg_err	3.890s	1.010ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.550s	253.218us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.550s	253.218us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.550s	253.218us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.550s	253.218us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.510s	486.135us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.890s	1.010ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.630s	2.479ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.120s	2.415ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.550s	253.218us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.720s	314.082us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.480s	205.957us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.330s	181.978us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.330s	131.862us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.330s	214.315us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	6.020s	1.160ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.920s	58.597us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	6.020s	1.160ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.660s	2.303ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	28.190m	452.544ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Past Results

• Latest
• lint
• 2024.02.22_04.49.41
• 2024.02.19_06.05.08
• 2024.02.14_21.54.23
• 2024.02.08_08.58.39
• 2024.02.05_04.38.54
• 2024.01.31_20.44.34