CLKMGR Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.650s	282.815us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.960s	25.926us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	21.310s	5.253ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.920s	94.706us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.390s	69.369us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
		clkmgr_csr_aliasing	1.920s	94.706us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.060s	137.114us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.560s	218.751us	50	50	100.00
V2	extclk	clkmgr_extclk	1.840s	363.119us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.150s	199.430us	50	50	100.00
V2	jitter	clkmgr_smoke	1.650s	282.815us	50	50	100.00
V2	frequency	clkmgr_frequency	17.740s	2.355ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.120s	2.055ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.740s	2.355ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.307m	18.831ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.810s	75.578us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.500s	247.234us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	7.410s	1.441ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	7.410s	1.441ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.960s	25.926us	5	5	100.00
		clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
		clkmgr_csr_aliasing	1.920s	94.706us	5	5	100.00
		clkmgr_same_csr_outstanding	1.870s	244.435us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.960s	25.926us	5	5	100.00
		clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
		clkmgr_csr_aliasing	1.920s	94.706us	5	5	100.00
		clkmgr_same_csr_outstanding	1.870s	244.435us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.410s	413.266us	5	5	100.00
		clkmgr_tl_intg_err	3.580s	508.692us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.530s	347.116us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.530s	347.116us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.530s	347.116us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.530s	347.116us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.900s	862.562us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.580s	508.692us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.740s	2.355ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.120s	2.055ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.530s	347.116us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.900s	328.345us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.820s	348.281us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.450s	227.005us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.240s	139.815us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.850s	360.556us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.410s	413.266us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.990s	51.203us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.410s	413.266us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.220s	2.701ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	44.983m	788.278ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.79	100.00	100.00	98.81	97.01	98.80

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