CLKMGR Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.400s 219.783us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.880s 50.045us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.180s 689.709us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.010s 139.881us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.960s 108.655us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
clkmgr_csr_aliasing 2.010s 139.881us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.970s 88.848us 50 50 100.00
V2 trans_enables clkmgr_trans 1.570s 227.157us 50 50 100.00
V2 extclk clkmgr_extclk 1.750s 320.997us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.090s 143.524us 50 50 100.00
V2 jitter clkmgr_smoke 1.400s 219.783us 50 50 100.00
V2 frequency clkmgr_frequency 18.760s 2.482ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.160s 2.413ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.760s 2.482ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.299m 10.803ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 94.034us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.050s 146.425us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.580s 1.042ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.580s 1.042ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.880s 50.045us 5 5 100.00
clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
clkmgr_csr_aliasing 2.010s 139.881us 5 5 100.00
clkmgr_same_csr_outstanding 2.150s 392.812us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.880s 50.045us 5 5 100.00
clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
clkmgr_csr_aliasing 2.010s 139.881us 5 5 100.00
clkmgr_same_csr_outstanding 2.150s 392.812us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.760s 611.192us 5 5 100.00
clkmgr_tl_intg_err 3.180s 224.681us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.520s 368.195us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.520s 368.195us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.520s 368.195us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.520s 368.195us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.450s 437.125us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.180s 224.681us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.760s 2.482ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.160s 2.413ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.520s 368.195us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.000s 421.984us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.180s 140.200us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.140s 81.484us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.670s 300.795us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.850s 335.285us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.760s 611.192us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.140s 124.759us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.760s 611.192us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 8.330s 1.356ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 32.639m 497.105ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.79 100.00 100.00 98.81 97.01 98.80

Past Results