CLKMGR Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.360s 176.663us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.150s 157.263us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.060s 497.699us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.320s 239.429us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.070s 44.239us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
clkmgr_csr_aliasing 2.320s 239.429us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.020s 109.721us 50 50 100.00
V2 trans_enables clkmgr_trans 1.490s 188.220us 50 50 100.00
V2 extclk clkmgr_extclk 1.460s 178.773us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.160s 183.172us 50 50 100.00
V2 jitter clkmgr_smoke 1.360s 176.663us 50 50 100.00
V2 frequency clkmgr_frequency 20.050s 2.481ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.060s 2.296ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 20.050s 2.481ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.369m 11.408ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 101.356us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.160s 158.056us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 9.960s 2.471ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 9.960s 2.471ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.150s 157.263us 5 5 100.00
clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
clkmgr_csr_aliasing 2.320s 239.429us 5 5 100.00
clkmgr_same_csr_outstanding 1.980s 437.777us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.150s 157.263us 5 5 100.00
clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
clkmgr_csr_aliasing 2.320s 239.429us 5 5 100.00
clkmgr_same_csr_outstanding 1.980s 437.777us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.390s 1.190ms 5 5 100.00
clkmgr_tl_intg_err 4.480s 821.856us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.470s 688.389us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.470s 688.389us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.470s 688.389us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.470s 688.389us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.010s 1.464ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.480s 821.856us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 20.050s 2.481ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.060s 2.296ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.470s 688.389us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.740s 282.764us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.870s 380.884us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.550s 277.836us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.620s 258.356us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.410s 208.526us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.390s 1.190ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.020s 85.608us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.390s 1.190ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.090s 1.228ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 36.242m 634.951ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results