CLKMGR Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.590s	273.806us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.160s	169.956us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.820s	431.567us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.920s	560.389us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.670s	149.813us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
		clkmgr_csr_aliasing	2.920s	560.389us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.220s	174.989us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.460s	210.332us	50	50	100.00
V2	extclk	clkmgr_extclk	1.770s	344.101us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.120s	184.004us	50	50	100.00
V2	jitter	clkmgr_smoke	1.590s	273.806us	50	50	100.00
V2	frequency	clkmgr_frequency	19.030s	2.477ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.510s	2.300ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.030s	2.477ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.460m	11.834ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.860s	96.238us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.180s	177.361us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.470s	783.235us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.470s	783.235us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.160s	169.956us	5	5	100.00
		clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
		clkmgr_csr_aliasing	2.920s	560.389us	5	5	100.00
		clkmgr_same_csr_outstanding	1.660s	224.764us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.160s	169.956us	5	5	100.00
		clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
		clkmgr_csr_aliasing	2.920s	560.389us	5	5	100.00
		clkmgr_same_csr_outstanding	1.660s	224.764us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.450s	488.948us	5	5	100.00
		clkmgr_tl_intg_err	6.790s	1.802ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.640s	418.055us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.640s	418.055us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.640s	418.055us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.640s	418.055us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.320s	308.891us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	6.790s	1.802ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.030s	2.477ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.510s	2.300ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.640s	418.055us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.960s	715.753us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.640s	272.784us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.630s	297.787us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.240s	120.173us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.660s	313.709us	49	50	98.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.450s	488.948us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.950s	77.554us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.450s	488.948us	5	5	100.00
V2S		TOTAL			314	315	99.68
V3	regwen	clkmgr_regwen	7.820s	1.399ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	34.211m	518.616ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Failure Buckets

• Offending '(gen_flops.gen_stable_chks.sig_unstable || (mubi_o == {NumCopies {$past(gen_flops.gen_stable_chks.mubi_in_sva_q, *)}}))' has 1 failures:

  • Test clkmgr_div_intersig_mubi has 1 failures.

    • 0.clkmgr_div_intersig_mubi.88010907779324072214469492483428903042614444408791639993010092210193092553544
      Line 250, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest/run.log

            Offending '(gen_flops.gen_stable_chks.sig_unstable || (mubi_o == {NumCopies {$past(gen_flops.gen_stable_chks.mubi_in_sva_q, 2)}}))'
        UVM_ERROR @   9372858 ps: (prim_mubi4_sync.sv:120) [ASSERT FAILED] OutputDelay_A
        UVM_INFO @   9372858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(step_down || maybe_divided_clk)' has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 37.clkmgr_stress_all_with_rand_reset.56312986472765039115757335442474387880128049575528535349273053711070051515907
      Line 353, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(step_down || maybe_divided_clk)'
        UVM_ERROR @ 3345150770 ps: (clkmgr_div_sva_if.sv:63) [ASSERT FAILED] Div4Whole_A
        UVM_INFO @ 3345150770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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