CLKMGR Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.560s	278.633us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.860s	55.680us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.580s	1.668ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.030s	73.915us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.590s	543.897us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
		clkmgr_csr_aliasing	2.030s	73.915us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.000s	129.109us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.250s	498.125us	50	50	100.00
V2	extclk	clkmgr_extclk	1.440s	221.000us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.210s	230.447us	50	50	100.00
V2	jitter	clkmgr_smoke	1.560s	278.633us	50	50	100.00
V2	frequency	clkmgr_frequency	18.850s	2.478ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.690s	2.177ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.850s	2.478ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.290m	16.203ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.920s	120.657us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.090s	69.516us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	9.860s	2.425ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	9.860s	2.425ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.860s	55.680us	5	5	100.00
		clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
		clkmgr_csr_aliasing	2.030s	73.915us	5	5	100.00
		clkmgr_same_csr_outstanding	3.010s	759.174us	19	20	95.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.860s	55.680us	5	5	100.00
		clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
		clkmgr_csr_aliasing	2.030s	73.915us	5	5	100.00
		clkmgr_same_csr_outstanding	3.010s	759.174us	19	20	95.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	clkmgr_sec_cm	18.610s	5.578ms	5	5	100.00
		clkmgr_tl_intg_err	5.470s	1.250ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.310s	298.870us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.310s	298.870us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.310s	298.870us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.310s	298.870us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.190s	1.124ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.470s	1.250ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.850s	2.478ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.690s	2.177ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.310s	298.870us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.060s	445.832us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.520s	251.898us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.160s	162.889us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.890s	364.387us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.610s	301.145us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	18.610s	5.578ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.040s	72.390us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	18.610s	5.578ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.080s	1.258ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	27.404m	400.917ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:
  • Test clkmgr_same_csr_outstanding has 1 failures.

    • 4.clkmgr_same_csr_outstanding.93239321330404531105192315223382008375240820804517684807766536270457675402182
      Line 257, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @   4424591 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @   4424591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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