CLKMGR Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.810s	376.893us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.960s	116.772us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.470s	1.698ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.570s	80.343us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.140s	114.663us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
		clkmgr_csr_aliasing	1.570s	80.343us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.160s	153.051us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.540s	204.777us	50	50	100.00
V2	extclk	clkmgr_extclk	1.330s	163.292us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.840s	65.097us	50	50	100.00
V2	jitter	clkmgr_smoke	1.810s	376.893us	50	50	100.00
V2	frequency	clkmgr_frequency	18.830s	2.476ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.840s	2.419ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.830s	2.476ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.786m	14.903ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.880s	103.533us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.260s	148.749us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.590s	352.427us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.590s	352.427us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.960s	116.772us	5	5	100.00
		clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
		clkmgr_csr_aliasing	1.570s	80.343us	5	5	100.00
		clkmgr_same_csr_outstanding	1.640s	180.844us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.960s	116.772us	5	5	100.00
		clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
		clkmgr_csr_aliasing	1.570s	80.343us	5	5	100.00
		clkmgr_same_csr_outstanding	1.640s	180.844us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.670s	1.423ms	5	5	100.00
		clkmgr_tl_intg_err	3.440s	440.721us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.630s	863.191us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.630s	863.191us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.630s	863.191us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.630s	863.191us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.700s	1.474ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.440s	440.721us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.830s	2.476ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.840s	2.419ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.630s	863.191us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.730s	260.950us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.410s	216.313us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.620s	294.354us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.330s	176.074us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.260s	126.378us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.670s	1.423ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.970s	90.796us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.670s	1.423ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.750s	1.380ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	27.327m	454.216ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.45	99.11	95.67	100.00	100.00	98.71	97.01	98.63

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