CLKMGR Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.810s	329.020us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.870s	30.185us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.410s	995.662us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.280s	483.827us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	3.150s	515.295us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
		clkmgr_csr_aliasing	2.280s	483.827us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.020s	115.030us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.230s	441.933us	50	50	100.00
V2	extclk	clkmgr_extclk	1.280s	160.173us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.840s	24.528us	50	50	100.00
V2	jitter	clkmgr_smoke	1.810s	329.020us	50	50	100.00
V2	frequency	clkmgr_frequency	18.510s	2.483ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.380s	2.299ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.510s	2.483ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.246m	9.812ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.950s	140.182us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.070s	123.381us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.750s	845.810us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.750s	845.810us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.870s	30.185us	5	5	100.00
		clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
		clkmgr_csr_aliasing	2.280s	483.827us	5	5	100.00
		clkmgr_same_csr_outstanding	1.600s	147.957us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.870s	30.185us	5	5	100.00
		clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
		clkmgr_csr_aliasing	2.280s	483.827us	5	5	100.00
		clkmgr_same_csr_outstanding	1.600s	147.957us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.260s	572.455us	5	5	100.00
		clkmgr_tl_intg_err	3.380s	819.331us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.330s	127.752us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.330s	127.752us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.330s	127.752us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.330s	127.752us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.280s	961.853us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.380s	819.331us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.510s	2.483ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.380s	2.299ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.330s	127.752us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.490s	228.122us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.250s	167.449us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.560s	284.057us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.500s	207.594us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.900s	392.055us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.260s	572.455us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.930s	22.782us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.260s	572.455us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.430s	1.345ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.267m	213.171ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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