CLKMGR Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.280s	158.793us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.020s	58.798us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	11.630s	1.785ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.220s	255.736us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.890s	217.533us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
		clkmgr_csr_aliasing	2.220s	255.736us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.020s	125.465us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.220s	470.241us	50	50	100.00
V2	extclk	clkmgr_extclk	1.940s	388.610us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.190s	210.066us	50	50	100.00
V2	jitter	clkmgr_smoke	1.280s	158.793us	50	50	100.00
V2	frequency	clkmgr_frequency	18.920s	2.364ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.200s	2.294ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.920s	2.364ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.552m	12.750ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.930s	118.107us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.430s	262.255us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.200s	455.190us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.200s	455.190us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.020s	58.798us	5	5	100.00
		clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
		clkmgr_csr_aliasing	2.220s	255.736us	5	5	100.00
		clkmgr_same_csr_outstanding	1.850s	207.156us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.020s	58.798us	5	5	100.00
		clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
		clkmgr_csr_aliasing	2.220s	255.736us	5	5	100.00
		clkmgr_same_csr_outstanding	1.850s	207.156us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	6.180s	1.486ms	5	5	100.00
		clkmgr_tl_intg_err	5.530s	1.260ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.590s	355.054us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.590s	355.054us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.590s	355.054us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.590s	355.054us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.640s	1.155ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.530s	1.260ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.920s	2.364ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.200s	2.294ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.590s	355.054us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.470s	197.902us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.540s	289.511us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.560s	272.735us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.280s	151.319us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.330s	183.538us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	6.180s	1.486ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.170s	166.986us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	6.180s	1.486ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.790s	1.338ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	1.079h	1.143s	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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