CSRNG Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	190.578us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	87.053us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	13.768us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.000s	980.016us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	164.932us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	82.126us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	13.768us	20	20	100.00
		csrng_csr_aliasing	6.000s	164.932us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	324.067us	200	200	100.00
V2	alerts	csrng_alert	10.000s	66.059us	500	500	100.00
V2	err	csrng_err	5.000s	19.754us	486	500	97.20
V2	cmds	csrng_cmds	5.967m	4.985ms	50	50	100.00
V2	life cycle	csrng_cmds	5.967m	4.985ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.483m	170.705ms	49	50	98.00
V2	intr_test	csrng_intr_test	5.000s	172.744us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	67.743us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	880.287us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	880.287us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	87.053us	5	5	100.00
		csrng_csr_rw	4.000s	13.768us	20	20	100.00
		csrng_csr_aliasing	6.000s	164.932us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	230.904us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	87.053us	5	5	100.00
		csrng_csr_rw	4.000s	13.768us	20	20	100.00
		csrng_csr_aliasing	6.000s	164.932us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	230.904us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	8.000s	120.383us	5	5	100.00
		csrng_tl_intg_err	9.000s	185.920us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	14.138us	50	50	100.00
		csrng_csr_rw	4.000s	13.768us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	10.000s	66.059us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.483m	170.705ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	10.000s	66.059us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.483m	170.705ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	10.000s	66.059us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	185.920us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
		csrng_sec_cm	8.000s	120.383us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	324.067us	200	200	100.00
		csrng_err	5.000s	19.754us	486	500	97.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.557h	412.445ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			1641	1670	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.64	93.16	84.12	95.28	86.30	91.94	100.00	97.33	94.74

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 1.csrng_stress_all_with_rand_reset.55297865924324203124078444515732203259920022367348497070180943692912251215204
    Line 402, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17325330632 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 17325330632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.csrng_stress_all_with_rand_reset.32867039393292709219528059562640984876101487037750172116159546033788030566836
    Line 821, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 452336483831 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 452336483831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

39.csrng_err.110184520856611007413296245886117990506081864161179604767751947861903537823449
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2005501 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2005501 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2005501 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2005501 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2005501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

209.csrng_err.110530449965025489561030759528128460961157781171802666845298589387966519230123
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/209.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1705059 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1705059 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1705059 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1705059 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1705059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

29.csrng_err.38869838385411591160796240983116638185892758365896310340408250835246664420294
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 13092534 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  13092534 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  13092534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

79.csrng_err.88986701483767143457276384090339068458276348667485806756977230885537180687365
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/79.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 10885034 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  10885034 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  10885034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 3.csrng_stress_all_with_rand_reset.45413812509303927506155931309739886109636607077649288446209134539953183102342
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9037703199 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 9037703199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.csrng_stress_all_with_rand_reset.55653652907031936224251239515850631865668931565218345621644478267578678096164
    Line 768, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 29408688906 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 29408688906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 8.csrng_stress_all_with_rand_reset.74096702620635105259834600775192548772572246992015152947923220666922176398072
    Line 400, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12892768379 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @ 12892768379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 37.csrng_stress_all.7258283622808871723964210980057203676588251556472347652571510877914477084176
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 10263263175 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10263263175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

433.csrng_err.51471283313012662715304156705046206012688353508992704543883136371272681167586
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/433.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  433.csrng_err.2231802594
  
  coverage files:
    model(design data) :  /workspace/coverage/default/433.csrng_err.2231802594/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/433.csrng_err.2231802594/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Feb 07, 2024 at 15:57:09 PST  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1