93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 110.597us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 4.000s | 18.094us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 20.000s | 1.059ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 7.000s | 305.509us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 7.000s | 356.445us | 4 | 20 | 20.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 4.000s | 18.094us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 7.000s | 305.509us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 39 | 105 | 37.14 | |||
| V2 | interrupts | csrng_intr | 0 | 200 | 0.00 | ||
| V2 | alerts | csrng_alert | 0 | 500 | 0.00 | ||
| V2 | err | csrng_err | 0 | 500 | 0.00 | ||
| V2 | cmds | csrng_cmds | 0 | 50 | 0.00 | ||
| V2 | life cycle | csrng_cmds | 0 | 50 | 0.00 | ||
| V2 | stress_all | csrng_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | csrng_intr_test | 4.000s | 79.027us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 10.000s | 201.640us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 10.000s | 201.640us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 110.597us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 18.094us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 7.000s | 305.509us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 6.000s | 378.701us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 110.597us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 18.094us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 7.000s | 305.509us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 6.000s | 378.701us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 1440 | 6.25 | |||
| V2S | tl_intg_err | csrng_sec_cm | 0 | 5 | 0.00 | ||
| csrng_tl_intg_err | 12.000s | 221.143us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 0 | 50 | 0.00 | ||
| csrng_csr_rw | 4.000s | 18.094us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 0 | 500 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 0 | 500 | 0.00 | ||
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 0 | 50 | 0.00 | ||
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 0 | 500 | 0.00 | ||
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 12.000s | 221.143us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| csrng_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 0 | 200 | 0.00 | ||
| csrng_err | 0 | 500 | 0.00 | ||||
| V2S | TOTAL | 20 | 75 | 26.67 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 149 | 1670 | 8.92 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 4 | 66.67 |
| V2 | 9 | 9 | 3 | 33.33 |
| V2S | 3 | 3 | 1 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 71.94 | 91.48 | 82.03 | 96.08 | 98.88 | 34.39 | -- | 100.00 | 23.49 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 753 failures:
0.csrng_smoke.52689258900162509215121600652975994374884757052769314695401428124625059700042
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
1.csrng_smoke.31749760524427943497354170767175830755361701296768933725171841143810251768201
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_smoke/latest/run.log
... and 26 more failures.
0.csrng_stress_all.26614966436386823625268456236357589435848381692413689751420786028443206593183
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
1.csrng_stress_all.49923713756484228221571169607802720507919938829507256976171311055485491280460
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
... and 26 more failures.
0.csrng_alert.111328058235860685546976523707436583541706418571152308052988567386234374524866
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_alert/latest/run.log
1.csrng_alert.46940506111165601198197627647056936246399556082651599780558282350730411339261
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_alert/latest/run.log
... and 101 more failures.
0.csrng_regwen.14297043820256473658531278479874973726242295944887639319992009860285309092350
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_regwen/latest/run.log
1.csrng_regwen.89801471470287858420706260270530769359565694195747985615363607204362727692851
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_regwen/latest/run.log
... and 26 more failures.
0.csrng_sec_cm.2051630420187198233359604440341621638105558747755416682560304677076116684444
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_sec_cm/latest/run.log
1.csrng_sec_cm.81714786259901294117514018413188796104461385366393969217820140477152375151146
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_sec_cm/latest/run.log
... and 3 more failures.
Job killed most likely because its dependent job failed. has 752 failures:
0.csrng_cmds.80299710431624155604405227670846989607128766088124355791696919281061946945839
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
1.csrng_cmds.71337411941517766631217141731485702965966652457057810644596657548019567404845
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_cmds/latest/run.log
... and 26 more failures.
0.csrng_intr.68327704512726419562653669913960008554879206983693995844632218414191926930368
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_intr/latest/run.log
1.csrng_intr.48655154157682996484745348918641641521998536965877566449723269255001159446931
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_intr/latest/run.log
... and 101 more failures.
0.csrng_err.66508512647253314592261296095501848395696190435743024766379644967884522980945
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_err/latest/run.log
1.csrng_err.100202234985450511553349003049391874468069622659593438682108313135979052838220
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_err/latest/run.log
... and 101 more failures.
0.csrng_stress_all_with_rand_reset.90526125439241346949886176715146366747588613197523026669682688031937152104797
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
1.csrng_stress_all_with_rand_reset.77478801581061618419388679752545210328512189250690625479284298160484694537217
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
... and 26 more failures.
0.csrng_alert_test.31795568208748927833541222131029666791347732688412224526426998123800070265352
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_alert_test/latest/run.log
1.csrng_alert_test.51191287123983748698151308025319481318304295176367375759314208871654884839001
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_alert_test/latest/run.log
... and 25 more failures.
UVM_ERROR (cip_base_vseq.sv:757) [csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 12 failures:
0.csrng_csr_mem_rw_with_rand_reset.70639281903953394328794162351159782765711222068755434887910884327015965242671
Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 32410713 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 32410713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_csr_mem_rw_with_rand_reset.104116392659880284628203301133110355782354453494326876243657576798621722992754
Line 275, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 15504897 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 15504897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 4 failures:
4.csrng_csr_mem_rw_with_rand_reset.99817678171779878074264447077543232947767417387170404586692193412881807792689
Line 275, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 148450212 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 148450212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.csrng_csr_mem_rw_with_rand_reset.91769026478076562351964464633040291036980097683004473721837569510213867973887
Line 275, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 38377239 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 38377239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.