CSRNG Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	207.796us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	236.703us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	58.783us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	11.000s	472.648us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	91.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	16.000s	636.368us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	58.783us	20	20	100.00
		csrng_csr_aliasing	4.000s	91.156us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	310.196us	200	200	100.00
V2	alerts	csrng_alert	8.000s	490.899us	500	500	100.00
V2	err	csrng_err	5.000s	20.356us	487	500	97.40
V2	cmds	csrng_cmds	5.967m	14.864ms	50	50	100.00
V2	life cycle	csrng_cmds	5.967m	14.864ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.009h	279.655ms	50	50	100.00
V2	intr_test	csrng_intr_test	4.000s	84.314us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	248.188us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	397.283us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	397.283us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	236.703us	5	5	100.00
		csrng_csr_rw	4.000s	58.783us	20	20	100.00
		csrng_csr_aliasing	4.000s	91.156us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	147.801us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	236.703us	5	5	100.00
		csrng_csr_rw	4.000s	58.783us	20	20	100.00
		csrng_csr_aliasing	4.000s	91.156us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	147.801us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	6.000s	76.802us	5	5	100.00
		csrng_tl_intg_err	14.000s	249.332us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	37.008us	50	50	100.00
		csrng_csr_rw	4.000s	58.783us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	490.899us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.009h	279.655ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	490.899us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.009h	279.655ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	490.899us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	249.332us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
		csrng_sec_cm	6.000s	76.802us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	310.196us	200	200	100.00
		csrng_err	5.000s	20.356us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.334h	95.464ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1607	1670	96.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.68	93.20	84.21	95.34	86.30	92.00	100.00	97.50	94.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:757) [csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 34 failures:
- Test csrng_stress_all_with_rand_reset has 34 failures.
  - 0.csrng_stress_all_with_rand_reset.29514096528900734198552380899068233366350786819438501766728561203228156776374
    Line 365, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20014086385 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 20014086385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.30615262726394014086415657192769113325742932389125160215998061567102739702271
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9252945223 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 9252945223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 16 failures:
- Test csrng_stress_all_with_rand_reset has 16 failures.
  - 3.csrng_stress_all_with_rand_reset.104437184510522505363214883929789008696897060484353780956558769567950534816160
    Line 671, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65399709677 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 65399709677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.91189224008617001490974643879186543585260137822627973053428211348640693756518
    Line 376, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29864274501 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 29864274501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 7 failures:

Test csrng_err has 7 failures.

30.csrng_err.81519488126745055293836258639194751403821669578284414814621034954373403946796
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 22468841 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 22468841 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 22468841 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  22468841 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  22468841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

172.csrng_err.90424924049876950441880522507224542944882840090160601161417379882584727813502
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/172.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2722368 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2722368 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2722368 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2722368 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2722368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed

has 5 failures:

Test csrng_err has 5 failures.

152.csrng_err.106713267847383643096230783517833757237417345226490550840741568095635267803194
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/152.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1733690 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1733690 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1733690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

197.csrng_err.44791808437722468166100556258525742845014036059447134383042298716258706683891
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/197.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 11181048 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  11181048 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  11181048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

246.csrng_err.58587808634871127017680239022744302614298654942389797815433242694875933370685
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/246.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  246.csrng_err.1364519229
  
  coverage files:
    model(design data) :  /workspace/coverage/default/246.csrng_err.1364519229/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/246.csrng_err.1364519229/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Feb 18, 2024 at 15:25:58 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1