CSRNG Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	171.768us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	15.497us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	269.596us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	30.000s	1.942ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	92.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	29.198us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	269.596us	20	20	100.00
		csrng_csr_aliasing	4.000s	92.117us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	5.000s	40.401us	200	200	100.00
V2	alerts	csrng_alert	10.000s	50.758us	500	500	100.00
V2	err	csrng_err	9.000s	28.107us	483	500	96.60
V2	cmds	csrng_cmds	6.483m	30.856ms	50	50	100.00
V2	life cycle	csrng_cmds	6.483m	30.856ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.017m	141.036ms	45	50	90.00
V2	intr_test	csrng_intr_test	7.000s	40.767us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	45.353us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	425.736us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	425.736us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	15.497us	5	5	100.00
		csrng_csr_rw	5.000s	269.596us	20	20	100.00
		csrng_csr_aliasing	4.000s	92.117us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	26.482us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	15.497us	5	5	100.00
		csrng_csr_rw	5.000s	269.596us	20	20	100.00
		csrng_csr_aliasing	4.000s	92.117us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	26.482us	20	20	100.00
V2		TOTAL			1418	1440	98.47
V2S	tl_intg_err	csrng_sec_cm	6.000s	259.897us	5	5	100.00
		csrng_tl_intg_err	17.000s	1.825ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	13.645us	50	50	100.00
		csrng_csr_rw	5.000s	269.596us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	10.000s	50.758us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.017m	141.036ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	10.000s	50.758us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.017m	141.036ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	10.000s	50.758us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	1.825ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
		csrng_sec_cm	6.000s	259.897us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	5.000s	40.401us	200	200	100.00
		csrng_err	9.000s	28.107us	483	500	96.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.362h	170.012ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1598	1670	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.72	93.22	84.25	95.36	86.34	92.00	98.18	97.50	95.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:775) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 26 failures:
- Test csrng_stress_all_with_rand_reset has 26 failures.
  - 1.csrng_stress_all_with_rand_reset.59784937115238756718677281478765598825315435480350823040368276494969240384710
    Line 400, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9300425899 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 9300425899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.90876658594764544612334798631662016196169923409088099871890394745746702272674
    Line 278, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 759507513 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 759507513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:775) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 24 failures:
- Test csrng_stress_all_with_rand_reset has 24 failures.
  - 0.csrng_stress_all_with_rand_reset.109970034314088502507619647943813839999641033774371839846029714439871606962137
    Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2398355208 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 2398355208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.43012667937916091765603731234755087550476067739046383107347090768502824247935
    Line 535, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31394015349 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 31394015349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

36.csrng_err.105450749761327477763675199547869757452248630971053709241675337841178848926019
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2022954 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2022954 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2022954 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2022954 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2022954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

90.csrng_err.102674757211039146558076815491435197239697455275303862782300771172949424614401
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/90.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6903483 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6903483 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6903483 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   6903483 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   6903483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

47.csrng_err.13694829710915065578788015362424024392804237709938441716357582281526657765743
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 6410111 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6410111 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6410111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

64.csrng_err.78116691861510271266128014607425554448999170211973321404238030670267846236280
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/64.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 14519114 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  14519114 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  14519114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
- Test csrng_stress_all has 4 failures.
  - 3.csrng_stress_all.44303061565334396400888362521100990853762783137898664317318195490220414577107
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 30836561599 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 30836561599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.csrng_stress_all.3326911053250954693617671611798963392179269335866269114510499219152907103655
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 25936369692 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 25936369692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

126.csrng_err.87449618299991325484897816287695207279078055948567595989016376042824824295069
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/126.csrng_err/latest/run.log

  UVM_ERROR @  17539700 ps: (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  17539700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

372.csrng_err.36869949753393272774322642193872762736683625517608049900174313321814186193304
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/372.csrng_err/latest/run.log

  UVM_ERROR @   3284719 ps: (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   3284719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

11.csrng_err.100665292235766642863311431232223916740946749256800686894614004135675609023324
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  11.csrng_err.1580008284
  
  coverage files:
    model(design data) :  /workspace/coverage/default/11.csrng_err.1580008284/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/11.csrng_err.1580008284/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Feb 21, 2024 at 15:42:36 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 37.csrng_stress_all.70783354586565009637721775845149729006054909474437164287895612786821128342542
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 11442883188 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 11442883188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```