CSRNG Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	200.464us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	35.770us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	155.608us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	13.000s	816.598us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	191.497us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	238.239us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	155.608us	20	20	100.00
		csrng_csr_aliasing	6.000s	191.497us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	33.810us	200	200	100.00
V2	alerts	csrng_alert	16.000s	178.472us	500	500	100.00
V2	err	csrng_err	13.000s	35.316us	486	500	97.20
V2	cmds	csrng_cmds	5.317m	22.241ms	50	50	100.00
V2	life cycle	csrng_cmds	5.317m	22.241ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.767m	87.366ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	14.676us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	64.758us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	452.057us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	452.057us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	35.770us	5	5	100.00
		csrng_csr_rw	4.000s	155.608us	20	20	100.00
		csrng_csr_aliasing	6.000s	191.497us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	446.588us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	35.770us	5	5	100.00
		csrng_csr_rw	4.000s	155.608us	20	20	100.00
		csrng_csr_aliasing	6.000s	191.497us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	446.588us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	6.000s	67.325us	5	5	100.00
		csrng_tl_intg_err	51.000s	1.095ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	14.305us	50	50	100.00
		csrng_csr_rw	4.000s	155.608us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.000s	178.472us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.767m	87.366ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.000s	178.472us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.767m	87.366ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.000s	178.472us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	51.000s	1.095ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
		csrng_sec_cm	6.000s	67.325us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	33.810us	200	200	100.00
		csrng_err	13.000s	35.316us	486	500	97.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.483h	173.903ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1604	1670	96.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.62	93.16	84.12	95.28	86.30	91.94	100.00	97.00	94.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:775) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 30 failures:
- Test csrng_stress_all_with_rand_reset has 30 failures.
  - 1.csrng_stress_all_with_rand_reset.105922268456474658245793218066618805017985657612587461775966475087659768138646
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14100640907 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 14100640907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.82966540810259047126028623402683042676287173146134151994211189285524508433896
    Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3206254233 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 3206254233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:775) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 20 failures:
- Test csrng_stress_all_with_rand_reset has 20 failures.
  - 0.csrng_stress_all_with_rand_reset.67153060258031348687420166315789813769717058865676327983586454566021296892410
    Line 306, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9074038785 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 9074038785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.112492819963742288836718686520583429886479687035120914414149170816356272525388
    Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118060727 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 118060727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

75.csrng_err.9313866283604573223344853350949712645849554704995331320964632206941446803778
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/75.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4013511 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4013511 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4013511 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4013511 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4013511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

149.csrng_err.20292971647954998177569624184907469229471914498593758399041638849350006621371
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/149.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1612498 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1612498 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1612498 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1612498 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1612498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 5 failures:
- Test csrng_err has 5 failures.
  - 90.csrng_err.111469959992974468363042348979168020830509451153990049726420197078710472651364
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/90.csrng_err/latest/run.log
```
  UVM_ERROR @  10658974 ps: (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  10658974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 91.csrng_err.44601082214946361883900892153368567607431758839636489490620462226620495672904
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/91.csrng_err/latest/run.log
```
  UVM_ERROR @   2536011 ps: (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   2536011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

274.csrng_err.52822397443386940464585208361697699604884434197185201495466264700771703556547
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/274.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 8675763 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8675763 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8675763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

469.csrng_err.42161813472367796004087575707176237838345509853370254120715734944036266404372
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/469.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 10752270 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  10752270 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  10752270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 3.csrng_stress_all.76089052532445597120730387758274954825567997963895015212030311747780594624745
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 240071950 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 240071950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 31.csrng_stress_all.78207500218616151430015975216900576265609246431266309624049788119684705329086
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/31.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 10561241438 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10561241438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): (time * NS) Assertion ValidKnown_A has failed has 1 failures:

Test csrng_err has 1 failures.

71.csrng_err.80660529481759635729682070378266850785083424372529250826117521939294370138789
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/71.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 28843 NS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 28843 NS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 28843 NS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  28843000 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  28843000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]