CSRNG Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	31.561us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	47.309us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	11.370us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	1.292ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	63.653us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	294.815us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	11.370us	20	20	100.00
		csrng_csr_aliasing	6.000s	63.653us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	48.187us	177	200	88.50
V2	alerts	csrng_alert	19.000s	42.751us	500	500	100.00
V2	err	csrng_err	15.000s	20.736us	474	500	94.80
V2	cmds	csrng_cmds	9.183m	47.389ms	50	50	100.00
V2	life cycle	csrng_cmds	9.183m	47.389ms	50	50	100.00
V2	stress_all	csrng_stress_all	39.917m	193.189ms	46	50	92.00
V2	intr_test	csrng_intr_test	4.000s	22.115us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	12.025us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	946.232us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	946.232us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	47.309us	5	5	100.00
		csrng_csr_rw	4.000s	11.370us	20	20	100.00
		csrng_csr_aliasing	6.000s	63.653us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	144.948us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	47.309us	5	5	100.00
		csrng_csr_rw	4.000s	11.370us	20	20	100.00
		csrng_csr_aliasing	6.000s	63.653us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	144.948us	20	20	100.00
V2		TOTAL			1387	1440	96.32
V2S	tl_intg_err	csrng_sec_cm	9.000s	40.673us	5	5	100.00
		csrng_tl_intg_err	9.000s	391.325us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	25.299us	50	50	100.00
		csrng_csr_rw	4.000s	11.370us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	19.000s	42.751us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	39.917m	193.189ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	19.000s	42.751us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	39.917m	193.189ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	19.000s	42.751us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	391.325us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
		csrng_sec_cm	9.000s	40.673us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	48.187us	177	200	88.50
		csrng_err	15.000s	20.736us	474	500	94.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.144h	280.303ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1567	1670	93.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.46	92.92	83.88	94.70	80.14	91.81	98.18	97.55	92.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test csrng_stress_all_with_rand_reset has 37 failures.
  - 0.csrng_stress_all_with_rand_reset.97510808250829812204716702314712910902284329813996271237158707549320792714839
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4503481645 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4503481645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.36945745254773374889589001523234784515869506358756129743491662119857425331681
    Line 439, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42315652087 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42315652087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed

has 20 failures:

Test csrng_intr has 20 failures.

14.csrng_intr.101561612137135111729198270517822933956403138655706554226823177140238041374129
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 51881017 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  51881017 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  51881017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.csrng_intr.114666982343542285641976083811955907347021875860642011329667077818185426778762
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 69050183 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  69050183 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  69050183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test csrng_stress_all_with_rand_reset has 13 failures.
  - 11.csrng_stress_all_with_rand_reset.91573935761950506023356010672256850970305657296400043366960649880651236356225
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11768861636 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11768861636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.csrng_stress_all_with_rand_reset.85644199352813116706744763104070717280827741171596789603223817373583077878513
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59674328004 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 59674328004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed

has 13 failures:

Test csrng_err has 13 failures.

122.csrng_err.19985358401175020958280565073083956441074156497712195834200224449652148807227
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/122.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3366624 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3366624 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3366624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

132.csrng_err.53764177744895962152214865738706585741207868646519977796045856771379645034229
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/132.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 16654180 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  16654180 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  16654180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:

Test csrng_err has 7 failures.

106.csrng_err.12516611770299439772320326416069418242305835782905597607577241508018972427026
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/106.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  106.csrng_err.3288761106
  
  coverage files:
    model(design data) :  /workspace/coverage/default/106.csrng_err.3288761106/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/106.csrng_err.3288761106/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 12, 2024 at 12:39:20 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

279.csrng_err.50999680233624323927107169692419237927817318951689257498869366510527830737846
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/279.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  279.csrng_err.746505142
  
  coverage files:
    model(design data) :  /workspace/coverage/default/279.csrng_err.746505142/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/279.csrng_err.746505142/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 12, 2024 at 12:40:09 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 6 failures:

Test csrng_err has 6 failures.

24.csrng_err.78824829935116660308061997316634588084303029097797578114370227819122661702959
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2270204 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2270204 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2270204 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2270204 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2270204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

377.csrng_err.110036321881680806542714880163324554855653686895400310278627946494067847687613
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/377.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 8468638 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 8468638 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 8468638 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   8468638 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   8468638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 10.csrng_stress_all.82989532909461911697654890749148896967472867425698174643174351358316600552217
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1843743894 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1843743894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.csrng_stress_all.108062710288052857209551426199278876067628679934396124344249665243149715985266
    Line 330, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1575871450 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1575871450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed

has 3 failures:

Test csrng_intr has 3 failures.

63.csrng_intr.66257625413205359374929910188190647177889572627870096350414371073596092272082
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/63.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 14489522 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 14489522 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  14489522 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  14489522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

84.csrng_intr.27076849891164352713094233001250193155208753725290366984027357957026002280001
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/84.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 17533951 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 17533951 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  17533951 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  17533951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 1.csrng_stress_all.39249693643815994353395685830545188174624675667779376255070778435727445278147
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1983377241 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1983377241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```