00fe426038| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 15.000s | 81.997us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 3.000s | 39.526us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 4.000s | 39.835us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 16.000s | 243.976us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 8.000s | 377.221us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 13.000s | 45.818us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 4.000s | 39.835us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 8.000s | 377.221us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| V2 | alerts | csrng_alert | 1.150m | 6.079ms | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 |
| V2 | cmds | csrng_cmds | 4.633m | 25.996ms | 38 | 50 | 76.00 |
| V2 | life cycle | csrng_cmds | 4.633m | 25.996ms | 38 | 50 | 76.00 |
| V2 | stress_all | csrng_stress_all | 15.833m | 37.835ms | 49 | 50 | 98.00 |
| V2 | intr_test | csrng_intr_test | 8.000s | 26.011us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 9.000s | 56.396us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 23.000s | 1.172ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 23.000s | 1.172ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 3.000s | 39.526us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 39.835us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 8.000s | 377.221us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 37.386us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 3.000s | 39.526us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 39.835us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 8.000s | 377.221us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 37.386us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1392 | 1440 | 96.67 | |||
| V2S | tl_intg_err | csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 12.000s | 386.695us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 14.000s | 19.099us | 50 | 50 | 100.00 |
| csrng_csr_rw | 4.000s | 39.835us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 1.150m | 6.079ms | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 15.833m | 37.835ms | 49 | 50 | 98.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 1.150m | 6.079ms | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 15.833m | 37.835ms | 49 | 50 | 98.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 1.150m | 6.079ms | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 12.000s | 386.695us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 11.000s | 103.062us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 20.000s | 192.395us | 180 | 200 | 90.00 |
| csrng_err | 19.000s | 22.379us | 485 | 500 | 97.00 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 50.233m | 84.064ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1572 | 1670 | 94.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 5 | 55.56 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.95 | 93.41 | 85.05 | 95.34 | 80.56 | 91.87 | 100.00 | 97.55 | 90.70 |
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
0.csrng_stress_all_with_rand_reset.96418255632384703270071783873670567120041707450838122059687858529219851901018
Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 147701070 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 147701070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.97634651006241865349803103093789710241276994911426522959295418655929540365234
Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 728147028 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 728147028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
1.csrng_stress_all_with_rand_reset.47298357796201294359034634031076326369257791511340827208602539978439931995916
Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 458078033 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 458078033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.csrng_stress_all_with_rand_reset.22372793088564963619934639727965795894736698751070289239400126750050633047326
Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6032609772 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6032609772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 17 failures:
22.csrng_intr.87310839004796308287537215882851439713460175746778658197132167241930104557188
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 15793508 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 15793508 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 15793508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.csrng_intr.92826338418410904048390719209983852865289215309003196712726019422644296513585
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 41440858 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 41440858 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 41440858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 8 failures:
5.csrng_cmds.94712527012761059055728091008518646377448393189846867726364489980267930740072
Line 383, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_cmds/latest/run.log
UVM_ERROR @ 1869696086 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 1869696086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.csrng_cmds.6160299054030576471318964639279519195659844224309988901787118914701934636860
Line 353, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_cmds/latest/run.log
UVM_ERROR @ 387393488 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 387393488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 7 failures:
43.csrng_err.112314465511052362585853130031866116478207077059666953084345943718307718427430
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6249235 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6249235 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6249235 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 6249235 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 6249235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
224.csrng_err.100138313863682528821687038127265989858223581506770087672882681047947808432162
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/224.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 10097371 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 10097371 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 10097371 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 10097371 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 10097371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 5 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:
47.csrng_err.32418665743586303567742622912260875298288359361816353916528103540995344928182
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 22055288 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 22055288 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 22055288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
190.csrng_err.35589434973238720893490872239961303221122052324601489580993404195573308743869
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/190.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2123253 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2123253 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2123253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 4 failures:
0.csrng_cmds.53720031564958088829281144158276122442995415697222902165707263883152902293833
Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
UVM_ERROR @ 507634161 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 507634161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_cmds.69598496810044461446692919941719085751410739428532026361640693889050603544264
Line 363, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_cmds/latest/run.log
UVM_ERROR @ 459592332 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 459592332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:
116.csrng_intr.108994151232759179274195157886447577177904578311802525384414303412888218863915
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/116.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 75743015 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 75743015 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 75743015 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 75743015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
150.csrng_intr.60564078401163872331865879147806827176816596147312176579592881892692308353693
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/150.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 42420837 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 42420837 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 42420837 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 42420837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
46.csrng_stress_all.95532698453815781999844256577726856870599173186782543140024336043848779709992
Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
UVM_ERROR @ 2788614793 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 2788614793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
163.csrng_err.104653456384147060594794291726256167252171151471446091898593940927717545896932
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/163.csrng_err/latest/run.log
UVM_ERROR @ 7753353 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 7753353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
359.csrng_err.112011105793668128852138285845995142521172259763752470896990183663745210715359
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/359.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 359.csrng_err.1579093215
coverage files:
model(design data) : /workspace/coverage/default/359.csrng_err.1579093215/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/359.csrng_err.1579093215/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 14, 2024 at 12:35:49 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1