349bab6601| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 9.000s | 61.834us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 69.949us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 4.000s | 28.905us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 30.000s | 1.486ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 10.000s | 46.611us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 5.000s | 155.054us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 4.000s | 28.905us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 10.000s | 46.611us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| V2 | alerts | csrng_alert | 1.000m | 4.957ms | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 |
| V2 | cmds | csrng_cmds | 10.033m | 58.886ms | 39 | 50 | 78.00 |
| V2 | life cycle | csrng_cmds | 10.033m | 58.886ms | 39 | 50 | 78.00 |
| V2 | stress_all | csrng_stress_all | 34.000m | 159.924ms | 46 | 50 | 92.00 |
| V2 | intr_test | csrng_intr_test | 8.000s | 14.501us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 8.000s | 29.815us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 17.000s | 886.019us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 17.000s | 886.019us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 69.949us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 28.905us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 10.000s | 46.611us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 6.000s | 237.346us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 69.949us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 28.905us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 10.000s | 46.611us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 6.000s | 237.346us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1387 | 1440 | 96.32 | |||
| V2S | tl_intg_err | csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 13.000s | 1.018ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 13.000s | 27.799us | 50 | 50 | 100.00 |
| csrng_csr_rw | 4.000s | 28.905us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 1.000m | 4.957ms | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 34.000m | 159.924ms | 46 | 50 | 92.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 1.000m | 4.957ms | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 34.000m | 159.924ms | 46 | 50 | 92.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 1.000m | 4.957ms | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 13.000s | 1.018ms | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| csrng_sec_cm | 9.000s | 126.039us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 18.000s | 10.456us | 182 | 200 | 91.00 |
| csrng_err | 8.000s | 26.996us | 480 | 500 | 96.00 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.002h | 161.270ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1567 | 1670 | 93.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 5 | 55.56 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.96 | 93.41 | 85.05 | 95.34 | 80.56 | 91.87 | 100.00 | 97.55 | 90.92 |
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
0.csrng_stress_all_with_rand_reset.54014696011968045183979028173086716132913470966085406625055925203655463107766
Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 583086072 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 583086072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.csrng_stress_all_with_rand_reset.3775951499701288449099195914689224645516101014717536156850607940018639513278
Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1376082317 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1376082317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
1.csrng_stress_all_with_rand_reset.41560451106189933156040704210963793937608898372943850154951422075679818449379
Line 567, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38779270579 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 38779270579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.28063018508975218925492775456611084528580313472754810083541345554815083589626
Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 188706134 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 188706134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 16 failures:
3.csrng_intr.20845607838610877350337696962222657458933940945487610482993857669046254970930
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 210241248 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 210241248 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 210241248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.csrng_intr.22269397376366703086153272247781114207623165912606736866462899917250273301670
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 34540088 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 34540088 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 34540088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 10 failures:
98.csrng_err.21937399260509483875380524704692487604459556764028771500047544260112656237413
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/98.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4652411 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4652411 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4652411 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 4652411 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 4652411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
130.csrng_err.21586817788731270049863714967099950164823176454194607949079939120515437494855
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/130.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1551610 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1551610 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1551610 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1551610 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1551610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 8 more failures.
UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 8 failures:
12.csrng_cmds.110935597254571282811008677303926998545187214476171972278354731527561260944960
Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_cmds/latest/run.log
UVM_ERROR @ 1572372088 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 1572372088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.csrng_cmds.37289552191074456822051026742612335813572578127981621818776088968159824707854
Line 353, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_cmds/latest/run.log
UVM_ERROR @ 3709166583 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 3709166583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:
161.csrng_err.109460139770007692297361471920792608787290787522250511630878134185728873965527
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/161.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2467857 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2467857 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2467857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
327.csrng_err.74692127888063876767663276119069088427526994025392922044834056736900034407461
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/327.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2458748 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2458748 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2458748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
143.csrng_err.85242573740001960578001145052712087351666840473444175289301211282988342030215
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/143.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 143.csrng_err.4251561863
coverage files:
model(design data) : /workspace/coverage/default/143.csrng_err.4251561863/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/143.csrng_err.4251561863/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 16, 2024 at 13:16:27 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
208.csrng_err.9763484832383908504369574384566640475363008607329792733008638843001234114716
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/208.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 208.csrng_err.3608004764
coverage files:
model(design data) : /workspace/coverage/default/208.csrng_err.3608004764/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/208.csrng_err.3608004764/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 16, 2024 at 13:22:05 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
... and 2 more failures.
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
0.csrng_stress_all.88583147003300902052458605718454603907543849429921930557550383742181982595960
Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
UVM_ERROR @ 5438673221 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 5438673221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.csrng_stress_all.58473785220760734451597687532607017690034980718707205676848677836237554935072
Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_stress_all/latest/run.log
UVM_ERROR @ 13685140689 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 13685140689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 2 failures:
10.csrng_cmds.82814839137777671351859419307493237870191755276730964246269382578632528554789
Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_cmds/latest/run.log
UVM_ERROR @ 171528473 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 171528473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.csrng_cmds.58922126997084110982210146744101546350481442898046963947257996530841950089200
Line 353, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_cmds/latest/run.log
UVM_ERROR @ 3574425065 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 3574425065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
38.csrng_stress_all.18544474123414445149933075421942809704453551116923418306236998786885477891933
Line 315, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log
UVM_ERROR @ 1484424310 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1484424310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.csrng_stress_all.68426557446621859290046893933907203462192751045164727682126145570291443572770
Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_stress_all/latest/run.log
UVM_ERROR @ 3147926937 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 3147926937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:
150.csrng_intr.26686174771314178891784774229604429672358048664690586512144664380921160648020
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/150.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 128115820 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 128115820 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 128115820 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 128115820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
189.csrng_intr.54443741859462249450488473165972721677526499401557631194587154290767960304605
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/189.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 108952116 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 108952116 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1724): (time 108952116 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1725): (time 108952116 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 108952116 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_FATAL (csrng_env_cfg.sv:283) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
6.csrng_cmds.46093995145847860560069221619019419978110964999628091293219875242526996993813
Line 374, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_cmds/latest/run.log
UVM_FATAL @ 1091130960 ps: (csrng_env_cfg.sv:283) [cfg] Check failed hw_v == v[app] (303155086420907439777922126478381998425 [0xe4118bbe577442195f4d5442dbd4e159] vs 0 [0x0])
UVM_INFO @ 1091130960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---