eb776817a5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 25.000s | 124.425us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 19.946us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 5.000s | 22.575us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 30.000s | 1.484ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 6.000s | 44.928us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 6.000s | 167.356us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 5.000s | 22.575us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 6.000s | 44.928us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| V2 | alerts | csrng_alert | 1.033m | 4.927ms | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 |
| V2 | cmds | csrng_cmds | 6.550m | 20.637ms | 36 | 50 | 72.00 |
| V2 | life cycle | csrng_cmds | 6.550m | 20.637ms | 36 | 50 | 72.00 |
| V2 | stress_all | csrng_stress_all | 34.200m | 75.016ms | 50 | 50 | 100.00 |
| V2 | intr_test | csrng_intr_test | 4.000s | 71.838us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 13.000s | 49.115us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 11.000s | 208.641us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 11.000s | 208.641us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 19.946us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 22.575us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 44.928us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 6.000s | 121.738us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 19.946us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 22.575us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 44.928us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 6.000s | 121.738us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1397 | 1440 | 97.01 | |||
| V2S | tl_intg_err | csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 1.500m | 3.374ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 9.000s | 45.004us | 50 | 50 | 100.00 |
| csrng_csr_rw | 5.000s | 22.575us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 1.033m | 4.927ms | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 34.200m | 75.016ms | 50 | 50 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 1.033m | 4.927ms | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 34.200m | 75.016ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 1.033m | 4.927ms | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 1.500m | 3.374ms | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 11.000s | 221.243us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 16.000s | 164.591us | 184 | 200 | 92.00 |
| csrng_err | 14.000s | 36.220us | 487 | 500 | 97.40 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 2.014h | 159.047ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1577 | 1670 | 94.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 6 | 66.67 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.90 | 93.38 | 84.97 | 95.30 | 80.53 | 91.74 | 98.18 | 97.39 | 90.70 |
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
2.csrng_stress_all_with_rand_reset.19157858883810808211108600199700509387655603481289788809108456184838624168624
Line 343, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7912273864 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7912273864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.csrng_stress_all_with_rand_reset.51650183807568343655559227771540553207549723197821463143005852970199439087661
Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39104062738 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 39104062738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
0.csrng_stress_all_with_rand_reset.112570002441465491112576452989242795124850120978973519268555773327471405880593
Line 349, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33027651952 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 33027651952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_stress_all_with_rand_reset.114977538744400984881967061282539992146601152194804892586142287720941710174451
Line 533, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75968088685 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 75968088685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 11 failures:
5.csrng_intr.71156611319652435044093865694846848431973300264410468792848011799052807943367
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 14903587 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 14903587 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 14903587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.csrng_intr.95970591496710265904577325657281860010500722966794487102700710622963155952463
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 33625913 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 33625913 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 33625913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 9 failures:
0.csrng_cmds.64451122146651407266376575950846819167002032199662019432999356150260956280911
Line 393, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
UVM_ERROR @ 2934793327 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 2934793327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_cmds.49188665909796150453679757554124572579975498992859729789115789027905939561501
Line 403, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_cmds/latest/run.log
UVM_ERROR @ 8613307054 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 8613307054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 5 failures:
61.csrng_err.66566447028284378080667964671150594435803804022875100998427793868003788555194
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/61.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 5223555 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 5223555 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5223555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
133.csrng_err.108723958587662346177335117975802240625195169215189450477644796059185575843289
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/133.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6878806 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 6878806 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 6878806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 5 failures:
94.csrng_intr.72064220284032552593909201142229640092006635763474751767680398149430584650894
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/94.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 14559642 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 14559642 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 14559642 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 14559642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
101.csrng_intr.8214748045489889677071357561795171985277519933646262175126514112059828810891
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 11228238 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 11228238 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 11228238 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 11228238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:
137.csrng_err.101007048800415219394421652191690270106966098384781654027931036576012690100627
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/137.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3354106 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3354106 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3354106 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 3354106 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 3354106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
246.csrng_err.17751520911396839833376657658341648325040237682901881662269414316732966491237
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/246.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1537105 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1537105 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1537105 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1537105 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1537105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 3 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 4 failures:
15.csrng_cmds.92741676215086150373630944230454646705538354910013419292433524075982338268492
Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_cmds/latest/run.log
UVM_ERROR @ 205909472 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 205909472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.csrng_cmds.20587646728567952971436956995293554968846833355978583935200915489601665058553
Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_cmds/latest/run.log
UVM_ERROR @ 512104104 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 512104104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:
79.csrng_err.85326540864378814671176065296745429062032626487930051932824554417678162186466
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/79.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 79.csrng_err.3345862882
coverage files:
model(design data) : /workspace/coverage/default/79.csrng_err.3345862882/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/79.csrng_err.3345862882/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 19, 2024 at 12:26:16 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
298.csrng_err.36234493674545117201056760796000479345229262920085101568439588913021306379761
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/298.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 298.csrng_err.1527619057
coverage files:
model(design data) : /workspace/coverage/default/298.csrng_err.1527619057/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/298.csrng_err.1527619057/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 19, 2024 at 12:27:51 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
... and 1 more failures.
UVM_FATAL (csrng_env_cfg.sv:282) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
20.csrng_cmds.41700024352127104787947406565957303325693419808666977057882662391488022895494
Line 384, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_cmds/latest/run.log
UVM_FATAL @ 8602380501 ps: (csrng_env_cfg.sv:282) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (4 [0x4] vs 0 [0x0])
UVM_INFO @ 8602380501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---