be3d980075| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 5.000s | 93.166us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 58.000us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 5.000s | 21.827us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 24.000s | 1.138ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 5.000s | 97.311us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 6.000s | 253.126us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 5.000s | 21.827us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 5.000s | 97.311us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| V2 | alerts | csrng_alert | 44.000s | 3.040ms | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 |
| V2 | cmds | csrng_cmds | 5.467m | 21.696ms | 46 | 50 | 92.00 |
| V2 | life cycle | csrng_cmds | 5.467m | 21.696ms | 46 | 50 | 92.00 |
| V2 | stress_all | csrng_stress_all | 21.350m | 81.681ms | 50 | 50 | 100.00 |
| V2 | intr_test | csrng_intr_test | 5.000s | 186.239us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 4.000s | 53.212us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 13.000s | 439.069us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 13.000s | 439.069us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 58.000us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 21.827us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 97.311us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 34.814us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 58.000us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 21.827us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 97.311us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 34.814us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1397 | 1440 | 97.01 | |||
| V2S | tl_intg_err | csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 17.000s | 1.492ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 4.000s | 11.295us | 50 | 50 | 100.00 |
| csrng_csr_rw | 5.000s | 21.827us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 44.000s | 3.040ms | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 21.350m | 81.681ms | 50 | 50 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 44.000s | 3.040ms | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 21.350m | 81.681ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 44.000s | 3.040ms | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 17.000s | 1.492ms | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| csrng_sec_cm | 7.000s | 107.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 7.000s | 375.848us | 176 | 200 | 88.00 |
| csrng_err | 4.000s | 32.139us | 485 | 500 | 97.00 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.485h | 100.621ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1577 | 1670 | 94.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 6 | 66.67 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.86 | 93.34 | 84.89 | 95.25 | 80.53 | 91.74 | 100.00 | 96.90 | 90.81 |
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
0.csrng_stress_all_with_rand_reset.9278832334162144956573131491999459510064525883794336764805364057513281924160
Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 255803785 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 255803785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.2460732178082056069194286190842320174922663290191210555957509669958620668669
Line 402, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45200269925 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 45200269925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 22 failures:
1.csrng_intr.36458507251260692204766780768535880204234770212342893372877692010871804141789
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 44118836 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 44118836 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 44118836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.csrng_intr.24306874588518753478767847107646428509351929048586657683275850133154451726219
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 29804978 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 29804978 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 29804978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
1.csrng_stress_all_with_rand_reset.50533060256977791941897110859859211395201154114834611687158197421398044015295
Line 356, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9103802893 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9103802893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.csrng_stress_all_with_rand_reset.105301297705181262023675649797613867565140507387039165848982914150042468697489
Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1489478650 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1489478650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 8 failures:
1.csrng_err.63135938253300756593678674208421440520896454362229138686210025462353457489126
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 5926343 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 5926343 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5926343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.csrng_err.57051589056971075752265773733975104887477468440650730997341218281790837967097
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 7741739 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 7741739 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 7741739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:
15.csrng_err.15355049448537483194061486187186531504271995659972123418894085309701647278356
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1580750 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1580750 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1580750 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1580750 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1580750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
72.csrng_err.65729181688389273438650966190316602457459705958773613181137303142022715079851
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/72.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1873884 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1873884 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1873884 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1873884 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1873884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 3 more failures.
UVM_ERROR (csrng_base_vseq.sv:119) [csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts) has 4 failures:
5.csrng_cmds.60061038389302886298804716561049573289558979006241019351815636509444938908750
Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_cmds/latest/run.log
UVM_ERROR @ 827182517 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 827182517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.csrng_cmds.83034355560410195808797382153115067319739253904303131419163902921776729078542
Line 403, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_cmds/latest/run.log
UVM_ERROR @ 1182951325 ps: (csrng_base_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.csrng_cmds_vseq] Check failed (cfg.m_edn_agent_cfg[app].vif.mon_cb.cmd_rsp.csrng_rsp_sts == exp_sts)
UVM_INFO @ 1182951325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:
39.csrng_intr.69229698018828836113823793679531719409896771539792251283295565936958834025495
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 59486688 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 59486688 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 59486688 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 59486688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
59.csrng_intr.111561856975614949710370722779859710066793380692404440017665130761796356791674
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/59.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 40665679 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 40665679 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 40665679 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 40665679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
167.csrng_err.100913263805944779968943098070397903581554431021342526038887259041374454147821
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/167.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 167.csrng_err.4155763437
coverage files:
model(design data) : /workspace/coverage/default/167.csrng_err.4155763437/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/167.csrng_err.4155763437/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 21, 2024 at 13:19:17 PDT (total: 00:00:04)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
305.csrng_err.74640291104171519358533496688490950017403994286604134942716954534333274625790
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/305.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 305.csrng_err.3073349374
coverage files:
model(design data) : /workspace/coverage/default/305.csrng_err.3073349374/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/305.csrng_err.3073349374/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 21, 2024 at 13:20:20 PDT (total: 00:00:04)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1